Lines Matching refs:pmu
87 static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
89 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
97 enable = pmu->enable;
155 struct i915_pmu *pmu = &i915->pmu;
166 spin_lock_irqsave(&pmu->lock, flags);
169 pmu->sample[__I915_SAMPLE_RC6].cur = val;
178 val = ktime_since(pmu->sleep_last);
179 val += pmu->sample[__I915_SAMPLE_RC6].cur;
182 if (val < pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur)
183 val = pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur;
185 pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur = val;
187 spin_unlock_irqrestore(&pmu->lock, flags);
194 struct i915_pmu *pmu = &i915->pmu;
196 if (pmu->enable & config_enabled_mask(I915_PMU_RC6_RESIDENCY))
197 pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(&i915->gt);
199 pmu->sleep_last = ktime_get();
213 static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu)
215 if (!pmu->timer_enabled && pmu_needs_timer(pmu, true)) {
216 pmu->timer_enabled = true;
217 pmu->timer_last = ktime_get();
218 hrtimer_start_range_ns(&pmu->timer,
226 struct i915_pmu *pmu = &i915->pmu;
228 if (!pmu->base.event_init)
231 spin_lock_irq(&pmu->lock);
239 pmu->timer_enabled = pmu_needs_timer(pmu, false);
241 spin_unlock_irq(&pmu->lock);
246 struct i915_pmu *pmu = &i915->pmu;
248 if (!pmu->base.event_init)
251 spin_lock_irq(&pmu->lock);
256 __i915_pmu_maybe_start_timer(pmu);
258 spin_unlock_irq(&pmu->lock);
284 if ((i915->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
291 struct intel_engine_pmu *pmu = &engine->pmu;
312 add_sample(&pmu->sample[I915_SAMPLE_WAIT], period_ns);
314 add_sample(&pmu->sample[I915_SAMPLE_SEMA], period_ns);
333 add_sample(&pmu->sample[I915_SAMPLE_BUSY], period_ns);
348 static bool frequency_sampling_enabled(struct i915_pmu *pmu)
350 return pmu->enable &
360 struct i915_pmu *pmu = &i915->pmu;
363 if (!frequency_sampling_enabled(pmu))
370 if (pmu->enable & config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY)) {
388 add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_ACT],
392 if (pmu->enable & config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY)) {
393 add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_REQ],
404 container_of(hrtimer, struct drm_i915_private, pmu.timer);
405 struct i915_pmu *pmu = &i915->pmu;
410 if (!READ_ONCE(pmu->timer_enabled))
414 period_ns = ktime_to_ns(ktime_sub(now, pmu->timer_last));
415 pmu->timer_last = now;
450 container_of(event->pmu, typeof(*i915), pmu.base);
520 container_of(event->pmu, typeof(*i915), pmu.base);
544 container_of(event->pmu, typeof(*i915), pmu.base);
547 if (event->attr.type != event->pmu->type)
580 container_of(event->pmu, typeof(*i915), pmu.base);
581 struct i915_pmu *pmu = &i915->pmu;
598 val = engine->pmu.sample[sample].cur;
604 div_u64(pmu->sample[__I915_SAMPLE_FREQ_ACT].cur,
609 div_u64(pmu->sample[__I915_SAMPLE_FREQ_REQ].cur,
642 container_of(event->pmu, typeof(*i915), pmu.base);
644 struct i915_pmu *pmu = &i915->pmu;
649 spin_lock_irqsave(&pmu->lock, flags);
655 BUILD_BUG_ON(ARRAY_SIZE(pmu->enable_count) != I915_PMU_MASK_BITS);
656 GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
657 GEM_BUG_ON(pmu->enable_count[bit] == ~0);
659 if (pmu->enable_count[bit] == 0 &&
661 pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur = 0;
662 pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(&i915->gt);
663 pmu->sleep_last = ktime_get();
666 pmu->enable |= BIT_ULL(bit);
667 pmu->enable_count[bit]++;
672 __i915_pmu_maybe_start_timer(pmu);
686 BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) !=
688 BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.sample) !=
690 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
691 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
692 GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
694 engine->pmu.enable |= BIT(sample);
695 engine->pmu.enable_count[sample]++;
698 spin_unlock_irqrestore(&pmu->lock, flags);
713 container_of(event->pmu, typeof(*i915), pmu.base);
715 struct i915_pmu *pmu = &i915->pmu;
718 spin_lock_irqsave(&pmu->lock, flags);
728 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
729 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
730 GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);
736 if (--engine->pmu.enable_count[sample] == 0)
737 engine->pmu.enable &= ~BIT(sample);
740 GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
741 GEM_BUG_ON(pmu->enable_count[bit] == 0);
746 if (--pmu->enable_count[bit] == 0) {
747 pmu->enable &= ~BIT_ULL(bit);
748 pmu->timer_enabled &= pmu_needs_timer(pmu, true);
751 spin_unlock_irqrestore(&pmu->lock, flags);
900 create_event_attributes(struct i915_pmu *pmu)
902 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
1015 pmu->i915_attr = i915_attr;
1016 pmu->pmu_attr = pmu_attr;
1032 static void free_event_attributes(struct i915_pmu *pmu)
1040 kfree(pmu->i915_attr);
1041 kfree(pmu->pmu_attr);
1044 pmu->i915_attr = NULL;
1045 pmu->pmu_attr = NULL;
1050 struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node);
1052 GEM_BUG_ON(!pmu->base.event_init);
1063 struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node);
1066 GEM_BUG_ON(!pmu->base.event_init);
1073 perf_pmu_migrate_context(&pmu->base, cpu, target);
1082 static int i915_pmu_register_cpuhp_state(struct i915_pmu *pmu)
1095 ret = cpuhp_state_add_instance(slot, &pmu->node);
1105 static void i915_pmu_unregister_cpuhp_state(struct i915_pmu *pmu)
1108 WARN_ON(cpuhp_state_remove_instance(cpuhp_slot, &pmu->node));
1125 struct i915_pmu *pmu = &i915->pmu;
1129 dev_info(i915->drm.dev, "PMU not supported for this GPU.");
1133 spin_lock_init(&pmu->lock);
1134 hrtimer_init(&pmu->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1135 pmu->timer.function = i915_sample;
1138 pmu->name = kasprintf(GFP_KERNEL,
1141 if (pmu->name) {
1143 strreplace((char *)pmu->name, ':', '_');
1146 pmu->name = "i915";
1148 if (!pmu->name)
1151 i915_pmu_events_attr_group.attrs = create_event_attributes(pmu);
1155 pmu->base.attr_groups = i915_pmu_attr_groups;
1156 pmu->base.task_ctx_nr = perf_invalid_context;
1157 pmu->base.event_init = i915_pmu_event_init;
1158 pmu->base.add = i915_pmu_event_add;
1159 pmu->base.del = i915_pmu_event_del;
1160 pmu->base.start = i915_pmu_event_start;
1161 pmu->base.stop = i915_pmu_event_stop;
1162 pmu->base.read = i915_pmu_event_read;
1163 pmu->base.event_idx = i915_pmu_event_event_idx;
1165 ret = perf_pmu_register(&pmu->base, pmu->name, -1);
1169 ret = i915_pmu_register_cpuhp_state(pmu);
1176 perf_pmu_unregister(&pmu->base);
1178 pmu->base.event_init = NULL;
1179 free_event_attributes(pmu);
1182 kfree(pmu->name);
1184 dev_notice(i915->drm.dev, "Failed to register PMU!\n");
1189 struct i915_pmu *pmu = &i915->pmu;
1191 if (!pmu->base.event_init)
1194 WARN_ON(pmu->enable);
1196 hrtimer_cancel(&pmu->timer);
1198 i915_pmu_unregister_cpuhp_state(pmu);
1200 perf_pmu_unregister(&pmu->base);
1201 pmu->base.event_init = NULL;
1203 kfree(pmu->name);
1204 free_event_attributes(pmu);
1205 spin_lock_destroy(&pmu->lock);
Indexes created Wed Oct 22 13:09:56 GMT 2025