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Lines Matching defs:dsparb

471 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
472 	((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
483 		u32 dsparb, dsparb2, dsparb3;
485 		dsparb = I915_READ(DSPARB);
487 		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
488 		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
491 		dsparb = I915_READ(DSPARB);
493 		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
494 		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
516 	u32 dsparb = I915_READ(DSPARB);
519 	size = dsparb & 0x7f;
521 		size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
524 		    dsparb, plane_name(i9xx_plane), size);
532 	u32 dsparb = I915_READ(DSPARB);
535 	size = dsparb & 0x1ff;
537 		size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
541 		    dsparb, plane_name(i9xx_plane), size);
549 	u32 dsparb = I915_READ(DSPARB);
552 	size = dsparb & 0x7f;
556 		    dsparb, plane_name(i9xx_plane), size);
1895 	 * DSPARB registers may have been reset due to the
1997 	 * it protects the DSPARB registers from getting clobbered by
2006 		u32 dsparb, dsparb2, dsparb3;
2008 		dsparb = intel_uncore_read_fw(uncore, DSPARB);
2011 		dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
2013 		dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
2021 		intel_uncore_write_fw(uncore, DSPARB, dsparb);
2025 		dsparb = intel_uncore_read_fw(uncore, DSPARB);
2028 		dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
2030 		dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
2038 		intel_uncore_write_fw(uncore, DSPARB, dsparb);
2062 	intel_uncore_posting_read_fw(uncore, DSPARB);