Cross Reference: /src/sys/external/bsd/drm2/dist/drm/i915/intel

Lines Matching defs:fbc
950  *  in the actual pixel depth regardless of whether FBC is enabled or not."
974 		   FW_WM(wm->sr.fbc, FBC_SR) |
975 		   FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
1204 	/* NORMAL level doesn't have an FBC watermark */
1210 		dirty |= raw->fbc != value;
1211 		raw->fbc = value;
1260 		 * FBC wm is not mandatory as we
1266 		dirty |= raw->fbc != wm;
1267 		raw->fbc = wm;
1287 				    "FBC watermarks: SR=%d, HPLL=%d\n",
1288 				    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
1289 				    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
1331 		wm_state->sr.fbc = USHRT_MAX;
1338 		wm_state->hpll.fbc = USHRT_MAX;
1388 	wm_state->sr.fbc = raw->fbc;
1400 	wm_state->hpll.fbc = raw->fbc;
1414 	 * Determine if the FBC watermark(s) can be used. IF
1415 	 * this isn't the case we prefer to disable the FBC
1422 	    wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
1425 		 wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
1470 	intermediate->sr.fbc = max(optimal->sr.fbc,
1471 				   active->sr.fbc);
1477 	intermediate->hpll.fbc = max(optimal->hpll.fbc,
1478 				     active->hpll.fbc);
1491 	WARN_ON(intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
1493 	WARN_ON(intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
2522 	u16 fbc;
2733 	max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2743 	max->fbc = ilk_fbc_wm_reg_max(dev_priv);
3328 	/* ILK: FBC WM must be disabled always */
3345 		 * FBC WMs instead of disabling a WM level.
3347 		if (wm->fbc_val > max->fbc) {
3354 	/* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3356 	 * FIXME this is racy. FBC might get enabled later.
3357 	 * What we should check here is whether FBC can be
5820 	wm->sr.fbc = _FW_WM(tmp, FBC_SR);
5821 	wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
5958 		raw->fbc = active->sr.fbc;
5967 		raw->fbc = active->hpll.fbc;
5987 		    "Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
5988 		    wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
5990 		    "Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
5991 		    wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
5992 	drm_dbg_kms(&dev_priv->drm, "Initial SR=%s HPLL=%s FBC=%s\n",
6029 				raw->fbc = 0;
6032 			wm_state->sr.fbc = 0;
6033 			wm_state->hpll.fbc = 0;
6358 	 * Required for FBC
6388 	 * should be set unconditionally in order to enable FBC.
6537 	 * set in order to enable memory self-refresh and fbc:
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