Home | History | Annotate | Download | only in i915

Lines Matching refs:hpll

435  * Certain platforms also have a deeper HPLL SR mode. Fortunately the
436  * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
437  * the hardware w.r.t. HPLL SR when writing to plane registers.
917 		/* Display HPLL off SR */
926 		/* cursor HPLL off SR */
975 		   FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
982 		   FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
983 		   FW_WM(wm->hpll.plane, HPLL_SR));
1148 	 * the HPLL watermark, which seems a little strange.
1149 	 * Let's use 32bpp for the HPLL watermark as well.
1279 			    "%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1287 				    "FBC watermarks: SR=%d, HPLL=%d\n",
1336 		wm_state->hpll.cursor = USHRT_MAX;
1337 		wm_state->hpll.plane = USHRT_MAX;
1338 		wm_state->hpll.fbc = USHRT_MAX;
1398 	wm_state->hpll.plane = raw->plane[PLANE_PRIMARY];
1399 	wm_state->hpll.cursor = raw->plane[PLANE_CURSOR];
1400 	wm_state->hpll.fbc = raw->fbc;
1416 	 ( watermark(s) rather than disable the SR/HPLL
1425 		 wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
1473 	intermediate->hpll.plane = max(optimal->hpll.plane,
1474 				       active->hpll.plane);
1475 	intermediate->hpll.cursor = max(optimal->hpll.cursor,
1476 					active->hpll.cursor);
1477 	intermediate->hpll.fbc = max(optimal->hpll.fbc,
1478 				     active->hpll.fbc);
1493 	WARN_ON(intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
1547 			wm->hpll = wm_state->hpll;
5821 	wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
5829 	wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
5830 	wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
5932 		active->hpll = wm->hpll;
5964 		raw->plane[PLANE_PRIMARY] = active->hpll.plane;
5965 		raw->plane[PLANE_CURSOR] = active->hpll.cursor;
5967 		raw->fbc = active->hpll.fbc;
5990 		    "Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
5991 		    wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
5992 	drm_dbg_kms(&dev_priv->drm, "Initial SR=%s HPLL=%s FBC=%s\n",
6033 			wm_state->hpll.fbc = 0;