Cross Reference: /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/hw.h

Lines Matching refs:head
39 void NVWriteVgaSeq(struct drm_device *, int head, uint8_t index, uint8_t value);
40 uint8_t NVReadVgaSeq(struct drm_device *, int head, uint8_t index);
41 void NVWriteVgaGr(struct drm_device *, int head, uint8_t index, uint8_t value);
42 uint8_t NVReadVgaGr(struct drm_device *, int head, uint8_t index);
44 void NVBlankScreen(struct drm_device *, int head, bool blank);
50 void nouveau_hw_save_state(struct drm_device *, int head,
52 void nouveau_hw_load_state(struct drm_device *, int head,
54 void nouveau_hw_load_state_palette(struct drm_device *, int head,
62 					int head, uint32_t reg)
66 	if (head)
73 					int head, uint32_t reg, uint32_t val)
76 	if (head)
82 					int head, uint32_t reg)
86 	if (head)
93 					int head, uint32_t reg, uint32_t val)
96 	if (head)
122 					int head, uint8_t index, uint8_t value)
125 	nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
126 	nvif_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
130 					int head, uint8_t index)
134 	nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
135 	val = nvif_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
141  * per-head variables around
154 NVWriteVgaCrtc5758(struct drm_device *dev, int head, uint8_t index, uint8_t value)
156 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index);
157 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_58, value);
160 static inline uint8_t NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_t index)
162 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index);
163 	return NVReadVgaCrtc(dev, head, NV_CIO_CRE_58);
167 					int head, uint32_t reg)
174 	 * NVSetOwner for the relevant head to be programmed */
175 	if (head && drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
183 					int head, uint32_t reg, uint8_t value)
189 	 * NVSetOwner for the relevant head to be programmed */
190 	if (head && drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
196 static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable)
199 	nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
200 	nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);
203 static inline bool NVGetEnablePalette(struct drm_device *dev, int head)
206 	nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
207 	return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);
211 					int head, uint8_t index, uint8_t value)
214 	if (NVGetEnablePalette(dev, head))
219 	nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
220 	nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
221 	nvif_wr08(device, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value);
225 					int head, uint8_t index)
229 	if (NVGetEnablePalette(dev, head))
234 	nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
235 	nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
236 	val = nvif_rd08(device, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE);
240 static inline void NVVgaSeqReset(struct drm_device *dev, int head, bool start)
242 	NVWriteVgaSeq(dev, head, NV_VIO_SR_RESET_INDEX, start ? 0x1 : 0x3);
245 static inline void NVVgaProtect(struct drm_device *dev, int head, bool protect)
247 	uint8_t seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
250 		NVVgaSeqReset(dev, head, true);
251 		NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
254 		NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);   /* reenable display */
255 		NVVgaSeqReset(dev, head, false);
257 	NVSetEnablePalette(dev, head, protect);
272 /* makes cr0-7 on the specified head read-only */
274 nv_lock_vga_crtc_base(struct drm_device *dev, int head, bool lock)
276 	uint8_t cr11 = NVReadVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX);
283 	NVWriteVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX, cr11);
289 nv_lock_vga_crtc_shadow(struct drm_device *dev, int head, int lock)
305 		cr21 = NVReadVgaCrtc(dev, head, NV_CIO_CRE_21) | 0xfa;
307 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_21, cr21);
343 nv_fix_nv40_hw_cursor(struct drm_device *dev, int head)
350 	uint32_t curpos = NVReadRAMDAC(dev, head, NV_PRAMDAC_CU_START_POS);
351 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_CU_START_POS, curpos);
355 nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset)
359 	NVWriteCRTC(dev, head, NV_PCRTC_START, offset);
366 		int cre_heb = NVReadVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX);
368 		NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX,
374 nv_show_cursor(struct drm_device *dev, int head, bool show)
378 		&nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
384 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1);
387 		nv_fix_nv40_hw_cursor(dev, head);