Lines Matching defs:ULONG
47 #ifndef ULONG
48 typedef unsigned long ULONG;
399 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
400 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
401 ULONG ulClockFreq:24;
403 ULONG ulClockFreq:24;
404 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
405 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
412 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
421 ULONG ulClock; //When return, [23:0] return real clock
446 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
447 ULONG ulClockFreq:24; // in unit of 10kHz
449 ULONG ulClockFreq:24; // in unit of 10kHz
450 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
465 ULONG ulClockParams; //ULONG access for BE
485 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
486 ULONG ulClock:24; //Input= target clock, output = actual clock
488 ULONG ulClock:24; //Input= target clock, output = actual clock
489 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
498 ULONG ulClockParams; //ULONG access for BE
515 ULONG ulReserved[2];
545 ULONG ulClock;
571 ULONG ulReserved[2];
577 ULONG ulMemoryClock;
578 ULONG ulReserved;
586 ULONG ulTargetEngineClock; //In 10Khz unit
591 ULONG ulTargetEngineClock; //In 10Khz unit
600 ULONG ulTargetMemoryClock; //In 10Khz unit
605 ULONG ulTargetMemoryClock; //In 10Khz unit
614 ULONG ulDefaultEngineClock; //In 10Khz unit
615 ULONG ulDefaultMemoryClock; //In 10Khz unit
670 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
1400 ULONG ulReserved[2];
1659 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1674 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1676 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1679 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1681 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1690 ULONG ulDispEngClkFreq; // dispclk frequency
1707 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1784 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
1815 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
1824 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
2004 ULONG ulTargetMemoryClock; //In 10Khz unit
2274 ULONG ulReserved;
2280 ULONG ulVotlageGpioState;
2281 ULONG ulVoltageGPioMask;
2289 ULONG ulReseved;
2313 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
2324 ULONG ulReseved;
2404 ULONG ulSignature; // HW info table signature string "$ATI"
2417 ULONG ulSignature; // MM info table signature sting "$MMT"
2511 ULONG ulFirmwareRevision;
2512 ULONG ulDefaultEngineClock; //In 10Khz unit
2513 ULONG ulDefaultMemoryClock; //In 10Khz unit
2514 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2515 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2516 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2517 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2518 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2519 ULONG ulASICMaxEngineClock; //In 10Khz unit
2520 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2523 ULONG aulReservedForBIOS[3]; //Don't use them
2545 ULONG ulFirmwareRevision;
2546 ULONG ulDefaultEngineClock; //In 10Khz unit
2547 ULONG ulDefaultMemoryClock; //In 10Khz unit
2548 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2549 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2550 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2551 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2552 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2553 ULONG ulASICMaxEngineClock; //In 10Khz unit
2554 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2558 ULONG aulReservedForBIOS[2]; //Don't use them
2559 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2581 ULONG ulFirmwareRevision;
2582 ULONG ulDefaultEngineClock; //In 10Khz unit
2583 ULONG ulDefaultMemoryClock; //In 10Khz unit
2584 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2585 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2586 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2587 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2588 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2589 ULONG ulASICMaxEngineClock; //In 10Khz unit
2590 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2594 ULONG aulReservedForBIOS; //Don't use them
2595 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2596 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2618 ULONG ulFirmwareRevision;
2619 ULONG ulDefaultEngineClock; //In 10Khz unit
2620 ULONG ulDefaultMemoryClock; //In 10Khz unit
2621 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2622 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2623 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2624 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2625 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2626 ULONG ulASICMaxEngineClock; //In 10Khz unit
2627 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2633 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2634 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2657 ULONG ulFirmwareRevision;
2658 ULONG ulDefaultEngineClock; //In 10Khz unit
2659 ULONG ulDefaultMemoryClock; //In 10Khz unit
2660 ULONG ulReserved1;
2661 ULONG ulReserved2;
2662 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2663 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2664 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2665 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
2666 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
2672 ULONG ulReserved4; //Was ulAsicMaximumVoltage
2673 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2698 ULONG ulFirmwareRevision;
2699 ULONG ulDefaultEngineClock; //In 10Khz unit
2700 ULONG ulDefaultMemoryClock; //In 10Khz unit
2701 ULONG ulSPLL_OutputFreq; //In 10Khz unit
2702 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
2703 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
2704 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
2705 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2706 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?
2707 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
2713 ULONG ulReserved4; //Was ulAsicMaximumVoltage
2714 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2717 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
2718 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
2731 ULONG ulReserved10[3]; // New added comparing to previous version
2752 ULONG ulBootUpEngineClock; //in 10kHz unit
2753 ULONG ulBootUpMemoryClock; //in 10kHz unit
2754 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
2755 ULONG ulMinSystemMemoryClock; //in 10kHz unit
2761 ULONG ulReserved[2];
2824 ULONG ulBootUpEngineClock; //in 10kHz unit
2825 ULONG ulReserved1[2]; //must be 0x0 for the reserved
2826 ULONG ulBootUpUMAClock; //in 10kHz unit
2827 ULONG ulBootUpSidePortClock; //in 10kHz unit
2828 ULONG ulMinSidePortClock; //in 10kHz unit
2829 ULONG ulReserved2[6]; //must be 0x0 for the reserved
2830 ULONG ulSystemConfig; //see explanation below
2831 ULONG ulBootUpReqDisplayVector;
2832 ULONG ulOtherDisplayMisc;
2833 ULONG ulDDISlot1Config;
2834 ULONG ulDDISlot2Config;
2839 ULONG ulDockingPinCFGInfo;
2840 ULONG ulCPUCapInfo;
2845 ULONG ulHTLinkFreq; //in 10Khz
2852 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
2853 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
2860 ULONG ulReserved3[96]; //must be 0x0
2997 ULONG ulBootUpEngineClock; //in 10kHz unit
2998 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
2999 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
3000 ULONG ulBootUpUMAClock; //in 10kHz unit
3001 ULONG ulReserved1[8]; //must be 0x0 for the reserved
3002 ULONG ulBootUpReqDisplayVector;
3003 ULONG ulOtherDisplayMisc;
3004 ULONG ulReserved2[4]; //must be 0x0 for the reserved
3005 ULONG ulSystemConfig; //TBD
3006 ULONG ulCPUCapInfo; //TBD
3012 ULONG ulReserved3[4]; //must be 0x0 for the reserved
3013 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
3014 ULONG ulDDISlot2Config;
3015 ULONG ulDDISlot3Config;
3016 ULONG ulDDISlot4Config;
3017 ULONG ulReserved4[4]; //must be 0x0 for the reserved
3021 ULONG ulReserved5[4]; //must be 0x0 for the reserved
3022 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
3023 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
3024 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
3025 ULONG ulReserved6[61]; //must be 0x0
3509 ULONG ulReserved0;
3547 ULONG ulReserved[2];
3852 ULONG ulStartAddrUsedByFirmware;
3866 ULONG ulStartAddrUsedByFirmware;
4228 ULONG ulACPIDeviceEnum; //Reserved for now
4328 ULONG ulStrengthControl; // DVOA strength control for CF
4586 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register
4604 ULONG ulReserved;
4619 ULONG ulGpioMaskVal; // GPIO Mask value
4629 ULONG ulMaxVoltageLevel;
4646 ULONG ulReserved;
4701 ULONG ulEvvDerateTdp;
4702 ULONG ulEvvDerateTdc;
4703 ULONG ulBoardCoreTemp;
4704 ULONG ulMaxVddc;
4705 ULONG ulMinVddc;
4706 ULONG ulLoadLineSlop;
4707 ULONG ulLeakageTemp;
4708 ULONG ulLeakageVoltage;
4709 ULONG ulCACmEncodeRange;
4710 ULONG ulCACmEncodeAverage;
4711 ULONG ulCACbEncodeRange;
4712 ULONG ulCACbEncodeAverage;
4713 ULONG ulKt_bEncodeRange;
4714 ULONG ulKt_bEncodeAverage;
4715 ULONG ulKv_mEncodeRange;
4716 ULONG ulKv_mEncodeAverage;
4717 ULONG ulKv_bEncodeRange;
4718 ULONG ulKv_bEncodeAverage;
4719 ULONG ulLkgEncodeLn_MaxDivMin;
4720 ULONG ulLkgEncodeMin;
4721 ULONG ulEfuseLogisticAlpha;
4776 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
4777 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4782 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4794 ULONG ulBootUpEngineClock;
4795 ULONG ulDentistVCOFreq;
4796 ULONG ulBootUpUMAClock;
4798 ULONG ulBootUpReqDisplayVector;
4799 ULONG ulOtherDisplayMisc;
4800 ULONG ulGPUCapInfo;
4801 ULONG ulSB_MMIO_Base_Addr;
4805 ULONG ulMinEngineClock;
4806 ULONG ulSystemConfig;
4807 ULONG ulCPUCapInfo;
4815 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];
4816 ULONG ulCSR_M3_ARB_CNTL_UVD[10];
4817 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];
4819 ULONG ulGMCRestoreResetTime;
4820 ULONG ulMinimumNClk;
4821 ULONG ulIdleNClk;
4822 ULONG ulDDR_DLL_PowerUpTime;
4823 ULONG ulDDR_PLL_PowerUpTime;
4832 ULONG SclkDpmBoostMargin;
4833 ULONG SclkDpmThrottleMargin;
4836 ULONG ulBoostEngineCLock;
4843 ULONG ulReserved3[15];
4957 ULONG ulPowerplayTable[128];
4964 ULONG uReserved:2;
4965 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
4966 ULONG uCTDP_Value:14; // Override value in tens of milli watts
4967 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
4969 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
4970 ULONG uCTDP_Value:14; // Override value in tens of milli watts
4971 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
4972 ULONG uReserved:2;
4979 ULONG TDP_config_all;
4992 ULONG ulBootUpEngineClock;
4993 ULONG ulDentistVCOFreq;
4994 ULONG ulBootUpUMAClock;
4996 ULONG ulBootUpReqDisplayVector;
4997 ULONG ulOtherDisplayMisc;
4998 ULONG ulGPUCapInfo;
4999 ULONG ulSB_MMIO_Base_Addr;
5003 ULONG ulMinEngineClock;
5004 ULONG ulSystemConfig;
5005 ULONG ulCPUCapInfo;
5015 ULONG ulReserved[19];
5017 ULONG ulGMCRestoreResetTime;
5018 ULONG ulMinimumNClk;
5019 ULONG ulIdleNClk;
5020 ULONG ulDDR_DLL_PowerUpTime;
5021 ULONG ulDDR_PLL_PowerUpTime;
5030 ULONG SclkDpmBoostMargin;
5031 ULONG SclkDpmThrottleMargin;
5034 ULONG ulBoostEngineCLock;
5049 ULONG ulLCDBitDepthControlVal;
5050 ULONG ulNbpStateMemclkFreq[4];
5053 ULONG ulNbpStateNClkFreq[4];
5219 ULONG ulBootUpEngineClock;
5220 ULONG ulDentistVCOFreq;
5221 ULONG ulBootUpUMAClock;
5223 ULONG ulBootUpReqDisplayVector;
5224 ULONG ulVBIOSMisc;
5225 ULONG ulGPUCapInfo;
5226 ULONG ulDISP_CLK2Freq;
5230 ULONG ulReserved2;
5231 ULONG ulSystemConfig;
5232 ULONG ulCPUCapInfo;
5233 ULONG ulReserved3;
5241 ULONG ulReserved[19];
5243 ULONG ulGMCRestoreResetTime;
5244 ULONG ulReserved4;
5245 ULONG ulIdleNClk;
5246 ULONG ulDDR_DLL_PowerUpTime;
5247 ULONG ulDDR_PLL_PowerUpTime;
5256 ULONG ulGPUReservedSysMemBaseAddrLo;
5257 ULONG ulGPUReservedSysMemBaseAddrHi;
5258 ULONG ulReserved5[3];
5270 ULONG ulLCDBitDepthControlVal;
5271 ULONG ulNbpStateMemclkFreq[4];
5272 ULONG ulReserved6;
5273 ULONG ulNbpStateNClkFreq[4];
5430 ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure
5474 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
5499 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5530 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
6006 ULONG ulTargetMemoryClock; //In 10Khz unit
6044 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position
6264 ULONG ulDllResetClkRange;
6270 ULONG ucMemBlkId:8;
6271 ULONG ulMemClockRange:24;
6273 ULONG ulMemClockRange:24;
6274 ULONG ucMemBlkId:8;
6281 ULONG ulAccess;
6287 ULONG aulMemData[1];
6309 #define VALUE_DWORD SIZEOF ULONG
6326 ULONG ulARB_SEQDataBuf[32];
6377 ULONG ulSignature;
6395 ULONG ulReserved;
6417 ULONG ulReserved;
6418 ULONG ulFlags; // To enable/disable functionalities based on memory type
6419 ULONG ulEngineClock; // Override of default engine clock for particular memory type
6420 ULONG ulMemoryClock; // Override of default memory clock for particular memory type
6445 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6481 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6514 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6550 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock
6577 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
6599 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
6641 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
6672 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
6704 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
6760 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
6854 ULONG Ptr32_Bit;
6899 ULONG RsvdOffScrnMemSize;
6900 ULONG RsvdOffScrnMEmPtr;
6914 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
6942 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer
6943 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
6958 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
7252 ULONG ulReserved;
7259 ULONG ulReserved;
7329 ULONG ulAnalogSetting[1];
7338 ULONG ulCondition;
7339 ULONG ulRegVal;
7343 ULONG ulCondition;
7345 ULONG ulRegVal;
7675 ULONG ulMiscInfo; //The power level should be arranged in ascending order
7676 ULONG ulReserved1; // must set to 0
7677 ULONG ulReserved2; // must set to 0
7691 ULONG ulMiscInfo; //The power level should be arranged in ascending order
7692 ULONG ulMiscInfo2;
7693 ULONG ulEngineClock;
7694 ULONG ulMemoryClock;
7706 ULONG ulMiscInfo; //The power level should be arranged in ascending order
7707 ULONG ulMiscInfo2;
7708 ULONG ulEngineClock;
7709 ULONG ulMemoryClock;
7922 ULONG Signature;
7923 ULONG TableLength; //Length
7928 ULONG OemRevision;
7929 ULONG CreatorId;
7930 ULONG CreatorRevision;
7949 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the structure.
7950 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the structure.
7951 ULONG Reserved[4]; //0x3C
7955 ULONG PCIBus; //0x4C
7956 ULONG PCIDevice; //0x50
7957 ULONG PCIFunction; //0x54
7962 ULONG Revision; //0x60
7963 ULONG ImageLength; //0x64
Indexes created Mon Oct 20 20:10:13 GMT 2025