Lines Matching defs:lvds
1635 struct radeon_encoder_atom_dig *lvds = NULL;
1642 lvds =
1645 if (!lvds)
1648 lvds->native_mode.clock =
1650 lvds->native_mode.hdisplay =
1652 lvds->native_mode.vdisplay =
1654 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1656 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1658 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1660 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1662 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1664 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1666 lvds->panel_pwr_delay =
1668 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1672 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1674 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1676 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1678 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1680 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1682 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1683 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1686 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1688 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1690 encoder->native_mode = lvds->native_mode;
1693 lvds->linkb = true;
1695 lvds->linkb = false;
1748 lvds->native_mode.width_mm = panel_res_record->usHSize;
1749 lvds->native_mode.height_mm = panel_res_record->usVSize;
1762 return lvds;