Lines Matching refs:RREG32
330 bus_cntl = RREG32(R600_BUS_CNTL);
331 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
332 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
333 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
334 rom_cntl = RREG32(R600_ROM_CNTL);
376 viph_control = RREG32(RADEON_VIPH_CONTROL);
377 bus_cntl = RREG32(R600_BUS_CNTL);
378 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
379 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
380 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
381 rom_cntl = RREG32(R600_ROM_CNTL);
398 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
407 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
422 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
449 viph_control = RREG32(RADEON_VIPH_CONTROL);
450 bus_cntl = RREG32(R600_BUS_CNTL);
451 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
452 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
453 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
454 rom_cntl = RREG32(R600_ROM_CNTL);
455 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
456 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
457 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
458 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
459 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
460 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
523 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
524 viph_control = RREG32(RADEON_VIPH_CONTROL);
525 bus_cntl = RREG32(RV370_BUS_CNTL);
526 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
527 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
528 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
529 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
530 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
531 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
582 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
583 viph_control = RREG32(RADEON_VIPH_CONTROL);
585 bus_cntl = RREG32(RV370_BUS_CNTL);
587 bus_cntl = RREG32(RADEON_BUS_CNTL);
588 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
590 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
594 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
598 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
Indexes created Thu Nov 06 07:09:58 GMT 2025