Lines Matching defs:macrotile
2349 u32 *macrotile = rdev->config.cik.macrotile_mode_array;
2379 macrotile[reg_offset] = 0;
2462 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2466 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2470 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2474 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2478 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2482 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2486 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2490 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2494 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2498 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2502 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2506 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2510 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2514 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2522 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2605 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2609 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2613 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2617 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2621 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2625 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2629 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2633 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2637 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2641 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2645 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2649 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2653 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2657 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2665 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2830 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2834 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2838 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2842 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2846 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2850 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2854 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2858 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2862 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2866 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2870 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2874 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2878 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2882 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2890 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2973 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2977 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2981 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2985 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2989 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2993 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2997 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3001 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3005 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3009 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3013 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3017 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3021 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3025 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3033 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
Indexes created Wed Oct 15 03:09:54 GMT 2025