Lines Matching defs:mqd
4374 dev_warn(rdev->dev, "(%d) reserve MQD bo failed\n", r);
4545 struct bonaire_mqd *mqd;
4597 dev_warn(rdev->dev, "(%d) create MQD bo failed\n", r);
4610 dev_warn(rdev->dev, "(%d) pin MQD bo failed\n", r);
4616 dev_warn(rdev->dev, "(%d) map MQD bo failed\n", r);
4621 /* init the mqd struct */
4624 mqd = (struct bonaire_mqd *)buf;
4625 mqd->header = 0xC0310800;
4626 mqd->static_thread_mgmt01[0] = 0xffffffff;
4627 mqd->static_thread_mgmt01[1] = 0xffffffff;
4628 mqd->static_thread_mgmt23[0] = 0xffffffff;
4629 mqd->static_thread_mgmt23[1] = 0xffffffff;
4642 mqd->queue_state.cp_hqd_pq_doorbell_control =
4645 mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;
4647 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_EN;
4649 mqd->queue_state.cp_hqd_pq_doorbell_control);
4652 mqd->queue_state.cp_hqd_dequeue_request = 0;
4653 mqd->queue_state.cp_hqd_pq_rptr = 0;
4654 mqd->queue_state.cp_hqd_pq_wptr= 0;
4662 WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
4663 WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
4664 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
4667 /* set the pointer to the MQD */
4668 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
4669 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
4670 WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
4671 WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
4672 /* set MQD vmid to 0 */
4673 mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL);
4674 mqd->queue_state.cp_mqd_control &= ~MQD_VMID_MASK;
4675 WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
4679 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
4680 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4681 WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
4682 WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
4685 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);
4686 mqd->queue_state.cp_hqd_pq_control &=
4689 mqd->queue_state.cp_hqd_pq_control |=
4691 mqd->queue_state.cp_hqd_pq_control |=
4694 mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;
4696 mqd->queue_state.cp_hqd_pq_control &=
4698 mqd->queue_state.cp_hqd_pq_control |=
4700 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
4707 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
4708 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4709 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
4711 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
4718 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
4719 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
4722 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
4724 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
4728 mqd->queue_state.cp_hqd_pq_doorbell_control =
4730 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_OFFSET_MASK;
4731 mqd->queue_state.cp_hqd_pq_doorbell_control |=
4733 mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;
4734 mqd->queue_state.cp_hqd_pq_doorbell_control &=
4738 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
4741 mqd->queue_state.cp_hqd_pq_doorbell_control);
4745 mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr;
4746 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
4747 mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR);
4750 mqd->queue_state.cp_hqd_vmid = 0;
4751 WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
4754 mqd->queue_state.cp_hqd_active = 1;
4755 WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
Indexes created Wed Oct 15 03:09:54 GMT 2025