Lines Matching refs:cik
1719 * (CIK).
1742 * requested doorbell index (CIK).
1767 * requested doorbell index (CIK).
1883 * Load the GDDR MC ucode into the hw (CIK).
2344 * surface uses those parameters (CIK).
2348 u32 *tile = rdev->config.cik.tile_mode_array;
2349 u32 *macrotile = rdev->config.cik.macrotile_mode_array;
2351 ARRAY_SIZE(rdev->config.cik.tile_mode_array);
2353 ARRAY_SIZE(rdev->config.cik.macrotile_mode_array);
2356 u32 num_rbs = rdev->config.cik.max_backends_per_se *
2357 cik.max_shader_engines;
2359 switch (rdev->config.cik.mem_row_size_in_kb) {
2372 num_pipe_configs = rdev->config.cik.max_tile_pipes;
3050 * broadcast to all SEs or SHs (CIK).
3073 * create a variable length bit mask (CIK).
3095 * Calculates the bitmask of disabled RBs (CIK).
3126 * Configures per-SE/SH RB registers (CIK).
3156 rdev->config.cik.backend_enable_mask = enabled_rbs;
3205 rdev->config.cik.max_shader_engines = 2;
3206 rdev->config.cik.max_tile_pipes = 4;
3207 rdev->config.cik.max_cu_per_sh = 7;
3208 rdev->config.cik.max_sh_per_se = 1;
3209 rdev->config.cik.max_backends_per_se = 2;
3210 rdev->config.cik.max_texture_channel_caches = 4;
3211 rdev->config.cik.max_gprs = 256;
3212 rdev->config.cik.max_gs_threads = 32;
3213 rdev->config.cik.max_hw_contexts = 8;
3215 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3216 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3217 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3218 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3222 rdev->config.cik.max_shader_engines = 4;
3223 rdev->config.cik.max_tile_pipes = 16;
3224 rdev->config.cik.max_cu_per_sh = 11;
3225 rdev->config.cik.max_sh_per_se = 1;
3226 rdev->config.cik.max_backends_per_se = 4;
3227 rdev->config.cik.max_texture_channel_caches = 16;
3228 rdev->config.cik.max_gprs = 256;
3229 rdev->config.cik.max_gs_threads = 32;
3230 rdev->config.cik.max_hw_contexts = 8;
3232 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3233 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3234 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3235 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3239 rdev->config.cik.max_shader_engines = 1;
3240 rdev->config.cik.max_tile_pipes = 4;
3241 rdev->config.cik.max_cu_per_sh = 8;
3242 rdev->config.cik.max_backends_per_se = 2;
3243 rdev->config.cik.max_sh_per_se = 1;
3244 rdev->config.cik.max_texture_channel_caches = 4;
3245 rdev->config.cik.max_gprs = 256;
3246 rdev->config.cik.max_gs_threads = 16;
3247 rdev->config.cik.max_hw_contexts = 8;
3249 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3250 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3251 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3252 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3258 rdev->config.cik.max_shader_engines = 1;
3259 rdev->config.cik.max_tile_pipes = 2;
3260 rdev->config.cik.max_cu_per_sh = 2;
3261 rdev->config.cik.max_sh_per_se = 1;
3262 rdev->config.cik.max_backends_per_se = 1;
3263 rdev->config.cik.max_texture_channel_caches = 2;
3264 rdev->config.cik.max_gprs = 256;
3265 rdev->config.cik.max_gs_threads = 16;
3266 rdev->config.cik.max_hw_contexts = 8;
3268 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3269 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3270 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3271 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3294 rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes;
3295 rdev->config.cik.mem_max_burst_length_bytes = 256;
3297 rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3298 if (rdev->config.cik.mem_row_size_in_kb > 4)
3299 rdev->config.cik.mem_row_size_in_kb = 4;
3301 rdev->config.cik.shader_engine_tile_size = 32;
3302 rdev->config.cik.num_gpus = 1;
3303 rdev->config.cik.multi_gpu_tile_size = 64;
3307 switch (rdev->config.cik.mem_row_size_in_kb) {
3327 rdev->config.cik.tile_config = 0;
3328 switch (rdev->config.cik.num_tile_pipes) {
3330 rdev->config.cik.tile_config |= (0 << 0);
3333 rdev->config.cik.tile_config |= (1 << 0);
3336 rdev->config.cik.tile_config |= (2 << 0);
3341 rdev->config.cik.tile_config |= (3 << 0);
3344 rdev->config.cik.tile_config |=
3346 rdev->config.cik.tile_config |=
3348 rdev->config.cik.tile_config |=
3362 cik_setup_rb(rdev, rdev->config.cik.max_shader_engines,
3363 rdev->config.cik.max_sh_per_se,
3364 rdev->config.cik.max_backends_per_se);
3366 rdev->config.cik.active_cus = 0;
3367 for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
3368 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
3369 rdev->config.cik.active_cus +=
3403 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |
3404 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |
3405 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |
3406 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));
3467 * Allocate a scratch register and write to it using the gfx ring (CIK).
3668 * Copy GPU paging using the CP DMA engine (CIK+).
3792 * Allocate an IB and execute it on the gfx ring (CIK).
3861 * On CIK, gfx and compute now have independant command processors.
4004 WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1);
4016 /* init the CE partitions. CE only used for gfx on CIK */
5273 * Check if the 3D engine is locked up (CIK).
5296 * physical address space (CIK).
5352 * vram and gart within the GPU's physical address space (CIK).
5424 * Flush the TLB for the VMID 0 page table (CIK).
5443 * and GPUVM for FSA64 clients (CIK).
5561 * This disables all VM page table (CIK).
5600 * Tears down the driver GART/VM setup (CIK).
5616 * CIK uses hw IB checking so this is a nop (CIK).
5630 * cik_vm_init - cik vm init callback
5634 * Inits cik specific vm parameters (number of VMs, base of vram for
5635 * VMIDs 1-15) (CIK).
5658 * cik_vm_fini - cik vm fini callback
5662 * Tear down any asic specific VM setup (CIK).
5675 * Print human readable fault information (CIK).
5698 * cik_vm_flush - cik vm flush using the CP
5703 * using the CP (CIK).
5814 for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
5815 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
5901 * Halt the RLC ME (MicroEngine) (CIK).
5917 * Unhalt the RLC ME (MicroEngine) (CIK).
5934 * and start the RLC (CIK).
6567 for (i = 0; i < rdev->config.cik.max_cu_per_sh; i ++) {
6581 for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
6582 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
6586 for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) {
6838 * Enable the interrupt ring buffer (CIK).
6857 * Disable the interrupt ring buffer (CIK).
6880 * Clear all interrupt enable bits used by the driver (CIK).
6959 * ring buffer and enable it (CIK).
7040 * etc.) (CIK).
7310 * etc.) (CIK). Certain interrupts sources are sw
7317 rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS);
7318 rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
7319 rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
7320 rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
7321 rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
7322 rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
7323 rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);
7325 rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +
7327 rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +
7330 rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +
7332 rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +
7336 rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +
7338 rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +
7342 if (rdev->irq.stat_regs.cik.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
7345 if (rdev->irq.stat_regs.cik.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
7348 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)
7350 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)
7352 if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
7354 if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT)
7358 if (rdev->irq.stat_regs.cik.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
7361 if (rdev->irq.stat_regs.cik.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
7364 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
7366 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
7368 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
7370 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
7375 if (rdev->irq.stat_regs.cik.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
7378 if (rdev->irq.stat_regs.cik.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
7381 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
7383 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
7385 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
7387 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
7391 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) {
7396 if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) {
7401 if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) {
7406 if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) {
7411 if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) {
7416 if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {
7421 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT) {
7426 if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT) {
7431 if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) {
7436 if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) {
7441 if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) {
7446 if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
7458 * Disable interrupts on the hw (CIK).
7474 * Disable interrupts and stop the RLC (CIK).
7489 * buffer (CIK).
7504 * or the writeback memory buffer (CIK). Also check for
7534 /* CIK IV Ring
7561 * Interrupt hander (CIK). Walk the IH ring,
7612 if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT))
7629 rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
7634 if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT))
7637 rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT;
7649 if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT))
7666 rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
7671 if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT))
7674 rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
7686 if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT))
7703 rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
7708 if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT))
7711 rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
7723 if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT))
7740 rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
7745 if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT))
7748 rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
7760 if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT))
7777 rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
7782 if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT))
7785 rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
7797 if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT))
7814 rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
7819 if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT))
7822 rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
7844 if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT))
7847 rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT;
7853 if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT))
7856 rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT;
7862 if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT))
7865 rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
7871 if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT))
7874 rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
7880 if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT))
7883 rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
7889 if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT))
7892 rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
7898 if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT))
7901 rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_RX_INTERRUPT;
7907 if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT))
7910 rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT;
7916 if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT))
7919 rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT;
7925 if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT))
7928 rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT;
7934 if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT))
7937 rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT;
7943 if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT))
7946 rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT;
8353 CIK).
8555 * Programs the asic to a functional state (CIK).
8575 DRM_ERROR("cik startup failed on resume\n");
8589 * Bring the chip into a state suitable for suspend (CIK).
8626 * to a functional state (CIK).
8776 * to an idle state (CIK).
8880 * the selected display controller (CIK).
8950 * Look up the number of video ram channels (CIK).
9002 * Calculate the raw dram bandwidth (CIK).
9031 * Calculate the dram bandwidth used for display (CIK).
9060 * Calculate the data return bandwidth used for display (CIK).
9089 * Calculate the dmif bandwidth used for display (CIK).
9120 * Calculate the min available bandwidth used for display (CIK).
9139 * Calculate the average available bandwidth used for display (CIK).
9172 * Calculate the latency watermark (CIK).
9233 * dram bandwidth (CIK).
9253 * available bandwidth (CIK).
9271 * Check latency hiding (CIK).
9310 * selected display controller (CIK).
9446 * buffer allocation (CIK).
Indexes created Sat Oct 18 21:09:54 GMT 2025