Lines Matching refs:mec
3878 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
4389 if (rdev->mec.hpd_eop_obj) {
4390 r = radeon_bo_reserve(rdev->mec.hpd_eop_obj, false);
4393 radeon_bo_unpin(rdev->mec.hpd_eop_obj);
4394 radeon_bo_unreserve(rdev->mec.hpd_eop_obj);
4396 radeon_bo_unref(&rdev->mec.hpd_eop_obj);
4397 rdev->mec.hpd_eop_obj = NULL;
4409 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
4410 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
4413 rdev->mec.num_mec = 2;
4415 rdev->mec.num_mec = 1;
4416 rdev->mec.num_pipe = 4;
4417 rdev->mec.num_queue = rdev->mec.num_mec * rdev->mec.num_pipe * 8;
4419 if (rdev->mec.hpd_eop_obj == NULL) {
4421 rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2,
4424 &rdev->mec.hpd_eop_obj);
4431 r = radeon_bo_reserve(rdev->mec.hpd_eop_obj, false);
4436 r = radeon_bo_pin(rdev->mec.hpd_eop_obj, RADEON_GEM_DOMAIN_GTT,
4437 &rdev->mec.hpd_eop_gpu_addr);
4443 r = radeon_bo_kmap(rdev->mec.hpd_eop_obj, (void **)&hpd);
4451 memset(hpd, 0, rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2);
4453 radeon_bo_kunmap(rdev->mec.hpd_eop_obj);
4454 radeon_bo_unreserve(rdev->mec.hpd_eop_obj);
4559 for (i = 0; i < (rdev->mec.num_pipe * rdev->mec.num_mec); ++i) {
4565 eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2) ;
4976 /* Disable MEC parsing/prefetching */
5180 /* Disable MEC parsing/prefetching */
8414 /* allocate mec buffers */
8417 DRM_ERROR("Failed to init MEC BOs!\n");
8485 /* type-2 packets are deprecated on MEC, use type-3 instead */
8491 ring->me = 1; /* first MEC */
8496 /* type-2 packets are deprecated on MEC, use type-3 instead */
8502 /* dGPU only have 1 MEC */
8503 ring->me = 1; /* first MEC */
Indexes created Mon Oct 20 11:09:49 GMT 2025