Lines Matching refs:tmp
205 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
208 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
210 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
398 uint32_t tmp;
405 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
406 tmp &= ~RADEON_DONT_USE_XTALIN;
407 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
409 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
410 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
411 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
415 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
416 tmp |= RADEON_SPLL_SLEEP;
417 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
421 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
422 tmp |= RADEON_SPLL_RESET;
423 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
427 tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
428 tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
429 tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
430 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
433 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
434 tmp &= ~RADEON_SPLL_PVG_MASK;
436 tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT);
438 tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT);
439 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
441 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
442 tmp &= ~RADEON_SPLL_SLEEP;
443 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
447 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
448 tmp &= ~RADEON_SPLL_RESET;
449 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
453 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
454 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
458 tmp |= 1;
461 tmp |= 2;
464 tmp |= 3;
467 tmp |= 4;
470 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
474 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
475 tmp |= RADEON_DONT_USE_XTALIN;
476 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
483 uint32_t tmp;
487 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
491 tmp &=
495 tmp &=
501 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
505 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
506 tmp &=
520 tmp |= RADEON_DYN_STOP_LAT_MASK;
521 tmp |=
524 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
526 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
527 tmp &= ~RADEON_SCLK_MORE_FORCEON;
528 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
529 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
531 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
532 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
534 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
536 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
537 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
550 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
552 tmp = RREG32_PLL(R300_SCLK_CNTL2);
553 tmp &= ~(R300_SCLK_FORCE_TCL |
556 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
559 WREG32_PLL(R300_SCLK_CNTL2, tmp);
561 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
562 tmp &=
576 tmp |= RADEON_DYN_STOP_LAT_MASK;
577 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
579 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
580 tmp &= ~RADEON_SCLK_MORE_FORCEON;
581 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
582 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
584 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
585 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
587 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
589 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
590 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
603 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
605 tmp = RREG32_PLL(RADEON_MCLK_MISC);
606 tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
608 WREG32_PLL(RADEON_MCLK_MISC, tmp);
610 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
611 tmp |= (RADEON_FORCEON_MCLKA |
614 tmp &= ~(RADEON_FORCEON_YCLKA |
622 if ((tmp & R300_DISABLE_MC_MCLKA) &&
623 (tmp & R300_DISABLE_MC_MCLKB)) {
625 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
629 tmp &=
632 tmp &=
635 tmp &= ~(R300_DISABLE_MC_MCLKA |
640 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
642 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
643 tmp &= ~(R300_SCLK_FORCE_VAP);
644 tmp |= RADEON_SCLK_FORCE_CP;
645 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
648 tmp = RREG32_PLL(R300_SCLK_CNTL2);
649 tmp &= ~(R300_SCLK_FORCE_TCL |
652 WREG32_PLL(R300_SCLK_CNTL2, tmp);
655 tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
657 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
661 tmp |= (RADEON_ENGIN_DYNCLK_MODE |
663 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
666 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
667 tmp |= RADEON_SCLK_DYN_START_CNTL;
668 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
674 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
675 /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */
676 tmp &= ~RADEON_SCLK_FORCEON_MASK;
688 tmp |= RADEON_SCLK_FORCE_CP;
689 tmp |= RADEON_SCLK_FORCE_VIP;
692 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
697 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
698 tmp &= ~RADEON_SCLK_MORE_FORCEON;
706 tmp |= RADEON_SCLK_MORE_FORCEON;
708 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
718 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
719 tmp |= RADEON_TCL_BYPASS_DISABLE;
720 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
725 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
726 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
734 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
737 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
738 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
741 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
747 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
748 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
755 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
758 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
759 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
767 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
769 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
770 tmp |= RADEON_SCLK_MORE_FORCEON;
771 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
773 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
774 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
777 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
779 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
780 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
794 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
797 tmp = RREG32_PLL(R300_SCLK_CNTL2);
798 tmp |= (R300_SCLK_FORCE_TCL |
800 WREG32_PLL(R300_SCLK_CNTL2, tmp);
802 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
803 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
811 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
813 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
814 tmp |= RADEON_SCLK_MORE_FORCEON;
815 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
817 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
818 tmp |= (RADEON_FORCEON_MCLKA |
822 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
824 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
825 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
828 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
830 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
831 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
845 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
847 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
848 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
849 tmp |= RADEON_SCLK_FORCE_SE;
852 tmp |= (RADEON_SCLK_FORCE_RB |
865 tmp |= (RADEON_SCLK_FORCE_HDP |
872 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
878 tmp = RREG32_PLL(R300_SCLK_CNTL2);
879 tmp |= (R300_SCLK_FORCE_TCL |
882 WREG32_PLL(R300_SCLK_CNTL2, tmp);
887 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
888 tmp &= ~(RADEON_FORCEON_MCLKA |
890 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
897 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
898 tmp |= RADEON_SCLK_MORE_FORCEON;
899 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
903 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
904 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
912 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
915 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
916 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
918 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);