Lines Matching defs:rdev
45 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
47 struct radeon_pll *spll = &rdev->clock.spll;
75 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
77 struct radeon_pll *mpll = &rdev->clock.mpll;
111 struct radeon_device *rdev = dev->dev_private;
112 struct device_node *dp = rdev->pdev->dev.of_node;
114 struct radeon_pll *p1pll = &rdev->clock.p1pll;
115 struct radeon_pll *p2pll = &rdev->clock.p2pll;
116 struct radeon_pll *spll = &rdev->clock.spll;
117 struct radeon_pll *mpll = &rdev->clock.mpll;
133 if (rdev->family >= CHIP_R420) {
153 rdev->clock.max_pixel_clock = 35000;
162 rdev->clock.default_sclk = (*val) / 10;
164 rdev->clock.default_sclk =
165 radeon_legacy_get_engine_clock(rdev);
169 rdev->clock.default_mclk = (*val) / 10;
171 rdev->clock.default_mclk =
172 radeon_legacy_get_memory_clock(rdev);
187 struct radeon_device *rdev = dev->dev_private;
188 struct radeon_pll *p1pll = &rdev->clock.p1pll;
189 struct radeon_pll *p2pll = &rdev->clock.p2pll;
190 struct radeon_pll *dcpll = &rdev->clock.dcpll;
191 struct radeon_pll *spll = &rdev->clock.spll;
192 struct radeon_pll *mpll = &rdev->clock.mpll;
195 if (rdev->is_atom_bios)
204 if (!ASIC_IS_AVIVO(rdev)) {
206 if (ASIC_IS_R300(rdev))
218 if (rdev->family < CHIP_RS600) {
227 if (ASIC_IS_AVIVO(rdev)) {
233 rdev->clock.max_pixel_clock = 35000;
235 if (rdev->flags & RADEON_IS_IGP) {
252 if (rdev->family >= CHIP_R420) {
276 rdev->clock.default_sclk =
277 radeon_legacy_get_engine_clock(rdev);
278 rdev->clock.default_mclk =
279 radeon_legacy_get_memory_clock(rdev);
284 if (ASIC_IS_AVIVO(rdev)) {
345 if (!rdev->clock.default_sclk)
346 rdev->clock.default_sclk = radeon_get_engine_clock(rdev);
347 if ((!rdev->clock.default_mclk) && rdev->asic->pm.get_memory_clock)
348 rdev->clock.default_mclk = radeon_get_memory_clock(rdev);
350 rdev->pm.current_sclk = rdev->clock.default_sclk;
351 rdev->pm.current_mclk = rdev->clock.default_mclk;
356 static uint32_t calc_eng_mem_clock(struct radeon_device *rdev,
360 struct radeon_pll *spll = &rdev->clock.spll;
395 void radeon_legacy_set_engine_clock(struct radeon_device *rdev,
403 eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div);
481 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
486 if (rdev->flags & RADEON_SINGLE_CRTC) {
502 } else if (ASIC_IS_R300(rdev)) {
503 if ((rdev->family == CHIP_RS400) ||
504 (rdev->family == CHIP_RS480)) {
551 } else if (rdev->family >= CHIP_RV350) {
626 if (rdev->mc.vram_width == 64) {
679 if (((rdev->family == CHIP_RV250) &&
683 || ((rdev->family == CHIP_RV100)
694 if ((rdev->family == CHIP_RV200) ||
695 (rdev->family == CHIP_RV250) ||
696 (rdev->family == CHIP_RV280)) {
701 if (((rdev->family == CHIP_RV200) ||
702 (rdev->family == CHIP_RV250)) &&
713 if (((rdev->family == CHIP_RV200) ||
714 (rdev->family == CHIP_RV250)) &&
746 if (rdev->flags & RADEON_SINGLE_CRTC) {
756 } else if ((rdev->family == CHIP_RS400) ||
757 (rdev->family == CHIP_RS480)) {
795 } else if (rdev->family >= CHIP_RV350) {
851 if (rdev->flags & RADEON_SINGLE_CRTC) {
863 } else if ((rdev->family == CHIP_R300) ||
864 (rdev->family == CHIP_R350)) {
876 if ((rdev->family == CHIP_R300) ||
877 (rdev->family == CHIP_R350)) {
886 if (rdev->flags & RADEON_IS_IGP) {
894 if ((rdev->family == CHIP_RV200) ||
895 (rdev->family == CHIP_RV250) ||
896 (rdev->family == CHIP_RV280)) {
Indexes created Thu Oct 02 07:10:07 GMT 2025