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Lines Matching refs:RBIOS32

756 		p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
757 		p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
762 			p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
763 			p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
773 		spll->pll_out_min = RBIOS32(pll_info + 0x1e);
774 		spll->pll_out_max = RBIOS32(pll_info + 0x22);
777 			spll->pll_in_min = RBIOS32(pll_info + 0x48);
778 			spll->pll_in_max = RBIOS32(pll_info + 0x4c);
788 		mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
789 		mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
792 			mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
793 			mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
811 		if (RBIOS32(pll_info + 0x16))
812 			rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
1223 		panel_setup = RBIOS32(lcd_info + 0x39);
1359 				    RBIOS32(tmds_info + i * 10 + 0x08);
1373 				    RBIOS32(tmds_info + stride + 0x08);
2574 								      RBIOS32(lcd_ddc_info + 3),
2575 								      RBIOS32(lcd_ddc_info + 7));
2582 								      RBIOS32(lcd_ddc_info + 3),
2583 								      RBIOS32(lcd_ddc_info + 7));
2742 			rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2743 			rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2917 						val = RBIOS32(index);
2923 						and_mask = RBIOS32(index);
2925 						or_mask = RBIOS32(index);
2972 					val = RBIOS32(index);
2977 					and_mask = RBIOS32(index);
2979 					or_mask = RBIOS32(index);
2992 					and_mask = RBIOS32(index);
2994 					or_mask = RBIOS32(index);
3034 				val = RBIOS32(offset);
3039 				val = RBIOS32(offset);
3044 				and_mask = RBIOS32(offset);
3046 				or_mask = RBIOS32(offset);
3054 				and_mask = RBIOS32(offset);
3056 				or_mask = RBIOS32(offset);
3113 				val = RBIOS32(offset);
3285 			mem_cntl = RBIOS32(offset + 1);