Lines Matching refs:lvds
1112 struct radeon_encoder_lvds *lvds = NULL;
1117 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1119 if (!lvds)
1126 lvds->panel_pwr_delay = 200;
1127 lvds->panel_vcc_delay = 2000;
1129 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1130 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1131 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1134 lvds->native_mode.vdisplay =
1138 lvds->native_mode.vdisplay =
1142 lvds->native_mode.hdisplay =
1146 lvds->native_mode.hdisplay =
1149 if ((lvds->native_mode.hdisplay < 640) ||
1150 (lvds->native_mode.vdisplay < 480)) {
1151 lvds->native_mode.hdisplay = 640;
1152 lvds->native_mode.vdisplay = 480;
1158 lvds->use_bios_dividers = false;
1160 lvds->panel_ref_divider =
1162 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1163 lvds->panel_fb_divider = ppll_val & 0x7ff;
1165 if ((lvds->panel_ref_divider != 0) &&
1166 (lvds->panel_fb_divider > 3))
1167 lvds->use_bios_dividers = true;
1169 lvds->panel_vcc_delay = 200;
1172 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1173 lvds->native_mode.vdisplay);
1175 return lvds;
1187 struct radeon_encoder_lvds *lvds = NULL;
1192 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1194 if (!lvds)
1203 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1204 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1206 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1207 lvds->native_mode.vdisplay);
1209 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1210 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1212 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1213 lvds
1214 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1216 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1217 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1218 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1219 if ((lvds->panel_ref_divider != 0) &&
1220 (lvds->panel_fb_divider > 3))
1221 lvds->use_bios_dividers = true;
1224 lvds->lvds_gen_cntl = 0xff00;
1226 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1229 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1233 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1236 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1239 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1246 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1249 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1252 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1255 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1257 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1264 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1265 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1268 if (hss > lvds->native_mode.hdisplay)
1271 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1273 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1275 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1278 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1280 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1282 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1285 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1286 lvds->native_mode.flags = 0;
1288 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1294 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1297 if (lvds)
1298 encoder->native_mode = lvds->native_mode;
1299 return lvds;
1564 /* LVDS */
1651 /* LVDS */
1692 /* LVDS */
1741 /* LVDS */
1789 /* LVDS */
2109 /* LVDS */
Indexes created Fri Nov 07 05:10:14 GMT 2025