Lines Matching refs:rdev
166 struct radeon_device *rdev = dev->dev_private;
168 if (rdev->flags & RADEON_IS_PX)
173 static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
179 if (rdev->pdev->vendor == p->chip_vendor &&
180 rdev->pdev->device == p->chip_device &&
181 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
182 rdev->pdev->subsystem_device == p->subsys_device) {
183 rdev->px_quirk_flags = p->px_quirk_flags;
189 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
190 rdev->flags &= ~RADEON_IS_PX;
195 rdev->flags &= ~RADEON_IS_PX;
201 * @rdev: radeon_device pointer
208 void radeon_program_register_sequence(struct radeon_device *rdev,
234 void radeon_pci_config_reset(struct radeon_device *rdev)
236 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
242 * @rdev: radeon_device pointer
246 void radeon_surface_init(struct radeon_device *rdev)
249 if (rdev->family < CHIP_R600) {
253 if (rdev->surface_regs[i].bo)
254 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
256 radeon_clear_surface_reg(rdev, i);
269 * @rdev: radeon_device pointer
273 void radeon_scratch_init(struct radeon_device *rdev)
278 if (rdev->family < CHIP_R300) {
279 rdev->scratch.num_reg = 5;
281 rdev->scratch.num_reg = 7;
283 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
284 for (i = 0; i < rdev->scratch.num_reg; i++) {
285 rdev->scratch.free[i] = true;
286 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
293 * @rdev: radeon_device pointer
299 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
303 for (i = 0; i < rdev->scratch.num_reg; i++) {
304 if (rdev->scratch.free[i]) {
305 rdev->scratch.free[i] = false;
306 *reg = rdev->scratch.reg[i];
316 * @rdev: radeon_device pointer
321 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
325 for (i = 0; i < rdev->scratch.num_reg; i++) {
326 if (rdev->scratch.reg[i] == reg) {
327 rdev->scratch.free[i] = true;
339 * @rdev: radeon_device pointer
344 static int radeon_doorbell_init(struct radeon_device *rdev)
351 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
352 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
354 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
355 if (rdev->doorbell.num_doorbells == 0)
360 rdev->doorbell.bst = rdev->pdev->pd_pa.pa_memt;
361 r = -bus_space_map(rdev->doorbell.bst, rdev->doorbell.base,
362 (rdev->doorbell.num_doorbells * sizeof(uint32_t)),
363 0, &rdev->doorbell.bsh);
367 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
368 if (rdev->doorbell.ptr == NULL) {
372 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
373 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
375 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
383 * @rdev: radeon_device pointer
387 static void radeon_doorbell_fini(struct radeon_device *rdev)
390 bus_space_unmap(rdev->doorbell.bst, rdev->doorbell.bsh,
391 (rdev->doorbell.num_doorbells * sizeof(uint32_t)));
393 iounmap(rdev->doorbell.ptr);
394 rdev->doorbell.ptr = NULL;
401 * @rdev: radeon_device pointer
407 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
409 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
410 if (offset < rdev->doorbell.num_doorbells) {
411 __set_bit(offset, rdev->doorbell.used);
422 * @rdev: radeon_device pointer
427 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
429 if (doorbell < rdev->doorbell.num_doorbells)
430 __clear_bit(doorbell, rdev->doorbell.used);
443 * @rdev: radeon_device pointer
447 void radeon_wb_disable(struct radeon_device *rdev)
449 rdev->wb.enabled = false;
455 * @rdev: radeon_device pointer
460 void radeon_wb_fini(struct radeon_device *rdev)
462 radeon_wb_disable(rdev);
463 if (rdev->wb.wb_obj) {
464 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
465 radeon_bo_kunmap(rdev->wb.wb_obj);
466 radeon_bo_unpin(rdev->wb.wb_obj);
467 radeon_bo_unreserve(rdev->wb.wb_obj);
469 radeon_bo_unref(&rdev->wb.wb_obj);
470 rdev->wb.wb = NULL;
471 rdev->wb.wb_obj = NULL;
478 * @rdev: radeon_device pointer
484 int radeon_wb_init(struct radeon_device *rdev)
488 if (rdev->wb.wb_obj == NULL) {
489 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
491 &rdev->wb.wb_obj);
493 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
496 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
498 radeon_wb_fini(rdev);
501 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
502 &rdev->wb.gpu_addr);
504 radeon_bo_unreserve(rdev->wb.wb_obj);
505 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
506 radeon_wb_fini(rdev);
509 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)__UNVOLATILE(&rdev->wb.wb));
510 radeon_bo_unreserve(rdev->wb.wb_obj);
512 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
513 radeon_wb_fini(rdev);
519 memset(__UNVOLATILE(rdev->wb.wb), 0, RADEON_GPU_PAGE_SIZE);
521 rdev->wb.use_event = false;
524 rdev->wb.enabled = false;
526 if (rdev->flags & RADEON_IS_AGP) {
528 rdev->wb.enabled = false;
529 } else if (rdev->family < CHIP_R300) {
531 rdev->wb.enabled = false;
533 rdev->wb.enabled = true;
535 if (rdev->family >= CHIP_R600) {
536 rdev->wb.use_event = true;
541 if (rdev->family >= CHIP_PALM) {
542 rdev->wb.enabled = true;
543 rdev->wb.use_event = true;
546 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
553 * @rdev: radeon device structure holding all necessary informations
592 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
597 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
598 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
603 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
604 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
611 dev_info(rdev->dev, "VRAM: %"PRIu64"M 0x%016"PRIX64" - 0x%016"PRIX64" (%"PRIu64"M used)\n",
618 * @rdev: radeon device structure holding all necessary informations
628 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
632 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
636 dev_warn(rdev->dev, "limiting GTT\n");
642 dev_warn(rdev->dev, "limiting GTT\n");
648 dev_info(rdev->dev, "GTT: %"PRIu64"M 0x%016"PRIX64" - 0x%016"PRIX64"\n",
679 * @rdev: radeon_device pointer
685 bool radeon_card_posted(struct radeon_device *rdev)
690 if (rdev->family >= CHIP_BONAIRE &&
697 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
698 (rdev->family < CHIP_R600))
702 if (ASIC_IS_NODCE(rdev))
706 if (ASIC_IS_DCE4(rdev)) {
709 if (rdev->num_crtc >= 4) {
713 if (rdev->num_crtc >= 6) {
719 } else if (ASIC_IS_AVIVO(rdev)) {
735 if (rdev->family >= CHIP_R600)
750 * @rdev: radeon_device pointer
755 void radeon_update_bandwidth_info(struct radeon_device *rdev)
758 u32 sclk = rdev->pm.current_sclk;
759 u32 mclk = rdev->pm.current_mclk;
763 rdev->pm.sclk.full = dfixed_const(sclk);
764 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
765 rdev->pm.mclk.full = dfixed_const(mclk);
766 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
768 if (rdev->flags & RADEON_IS_IGP) {
771 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
778 * @rdev: radeon_device pointer
784 bool radeon_boot_test_post_card(struct radeon_device *rdev)
786 if (radeon_card_posted(rdev))
789 if (rdev->bios) {
791 if (rdev->is_atom_bios)
792 atom_asic_init(rdev->mode_info.atom_context);
794 radeon_combios_asic_init(rdev->ddev);
797 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
805 * @rdev: radeon_device pointer
812 int radeon_dummy_page_init(struct radeon_device *rdev)
819 if (rdev->dummy_page.rdp_map != NULL)
822 error = bus_dmamem_alloc(rdev->ddev->dmat, PAGE_SIZE, PAGE_SIZE, 0,
823 &rdev->dummy_page.rdp_seg, 1, &rsegs, BUS_DMA_WAITOK);
827 error = bus_dmamap_create(rdev->ddev->dmat, PAGE_SIZE, 1, PAGE_SIZE, 0,
828 BUS_DMA_WAITOK, &rdev->dummy_page.rdp_map);
831 error = bus_dmamem_map(rdev->ddev->dmat, &rdev->dummy_page.rdp_seg, 1,
832 PAGE_SIZE, &rdev->dummy_page.rdp_addr,
836 error = bus_dmamap_load(rdev->ddev->dmat, rdev->dummy_page.rdp_map,
837 rdev->dummy_page.rdp_addr, PAGE_SIZE, NULL, BUS_DMA_WAITOK);
841 memset(rdev->dummy_page.rdp_addr, 0, PAGE_SIZE);
842 bus_dmamap_sync(rdev->ddev->dmat, rdev->dummy_page.rdp_map, 0,
846 rdev->dummy_page.addr = rdev->dummy_page.rdp_map->dm_segs[0].ds_addr;
847 rdev->dummy_page.entry = radeon_gart_get_page_entry(
848 rdev->dummy_page.addr, RADEON_GART_PAGE_DUMMY);
852 bus_dmamap_unload(rdev->ddev->dmat, rdev->dummy_page.rdp_map);
853 fail3: bus_dmamem_unmap(rdev->ddev->dmat, rdev->dummy_page.rdp_addr,
855 fail2: bus_dmamap_destroy(rdev->ddev->dmat, rdev->dummy_page.rdp_map);
856 fail1: bus_dmamem_free(rdev->ddev->dmat, &rdev->dummy_page.rdp_seg, 1);
858 rdev->dummy_page.rdp_map = NULL;
862 if (rdev->dummy_page.page)
864 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
865 if (rdev->dummy_page.page == NULL)
867 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
869 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
870 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
871 __free_page(rdev->dummy_page.page);
872 rdev->dummy_page.page = NULL;
875 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr,
884 * @rdev: radeon_device pointer
888 void radeon_dummy_page_fini(struct radeon_device *rdev)
892 if (rdev->dummy_page.rdp_map == NULL)
894 bus_dmamap_unload(rdev->ddev->dmat, rdev->dummy_page.rdp_map);
895 bus_dmamem_unmap(rdev->ddev->dmat, rdev->dummy_page.rdp_addr,
897 bus_dmamap_destroy(rdev->ddev->dmat, rdev->dummy_page.rdp_map);
898 bus_dmamem_free(rdev->ddev->dmat, &rdev->dummy_page.rdp_seg, 1);
899 rdev->dummy_page.rdp_map = NULL;
901 if (rdev->dummy_page.page == NULL)
903 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
905 __free_page(rdev->dummy_page.page);
906 rdev->dummy_page.page = NULL;
931 struct radeon_device *rdev = info->dev->dev_private;
934 r = rdev->pll_rreg(rdev, reg);
949 struct radeon_device *rdev = info->dev->dev_private;
951 rdev->pll_wreg(rdev, reg, val);
965 struct radeon_device *rdev = info->dev->dev_private;
968 r = rdev->mc_rreg(rdev, reg);
983 struct radeon_device *rdev = info->dev->dev_private;
985 rdev->mc_wreg(rdev, reg, val);
999 struct radeon_device *rdev = info->dev->dev_private;
1015 struct radeon_device *rdev = info->dev->dev_private;
1033 struct radeon_device *rdev = info->dev->dev_private;
1049 struct radeon_device *rdev = info->dev->dev_private;
1059 * @rdev: radeon_device pointer
1066 int radeon_atombios_init(struct radeon_device *rdev)
1074 rdev->mode_info.atom_card_info = atom_card_info;
1075 atom_card_info->dev = rdev->ddev;
1080 if (rdev->rio_mem_size)
1082 if (rdev->rio_mem)
1097 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
1098 if (!rdev->mode_info.atom_context) {
1099 radeon_atombios_fini(rdev);
1103 mutex_init(&rdev->mode_info.atom_context->mutex);
1104 mutex_init(&rdev->mode_info.atom_context->scratch_mutex);
1105 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
1106 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
1113 * @rdev: radeon_device pointer
1119 void radeon_atombios_fini(struct radeon_device *rdev)
1121 if (rdev->mode_info.atom_context) {
1122 mutex_destroy(&rdev->mode_info.atom_context->scratch_mutex);
1123 mutex_destroy(&rdev->mode_info.atom_context->mutex);
1124 kfree(rdev->mode_info.atom_context->scratch);
1126 kfree(rdev->mode_info.atom_context);
1127 rdev->mode_info.atom_context = NULL;
1128 kfree(rdev->mode_info.atom_card_info);
1129 rdev->mode_info.atom_card_info = NULL;
1142 * @rdev: radeon_device pointer
1148 int radeon_combios_init(struct radeon_device *rdev)
1150 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1157 * @rdev: radeon_device pointer
1162 void radeon_combios_fini(struct radeon_device *rdev)
1179 struct radeon_device *rdev = cookie;
1180 radeon_vga_set_state(rdev, state);
1221 * @rdev: radeon_device pointer
1226 static void radeon_check_arguments(struct radeon_device *rdev)
1230 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1236 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1240 dev_warn(rdev->dev, "gart size (%d) too small\n",
1242 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1244 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1246 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1248 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1260 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1267 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
1273 dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n",
1282 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
1303 dev_warn(rdev->dev, "VM page table size (%d) too small\n",
1310 dev_warn(rdev->dev, "VM page table size (%d) too large\n",
1382 * @rdev: radeon_device pointer
1391 int radeon_device_init(struct radeon_device *rdev,
1402 rdev->shutdown = false;
1403 rdev->dev = ddev->dev;
1404 rdev->ddev = ddev;
1405 rdev->pdev = pdev;
1406 rdev->flags = flags;
1407 rdev->family = flags & RADEON_FAMILY_MASK;
1408 rdev->is_atom_bios = false;
1409 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1410 rdev->mc.gtt_size = 512 * 1024 * 1024;
1411 rdev->accel_working = false;
1414 rdev->ring[i].idx = i;
1416 rdev->fence_context = dma_fence_context_alloc(RADEON_NUM_RINGS);
1419 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1424 mutex_init(&rdev->ring_lock);
1425 mutex_init(&rdev->dc_hw_i2c_mutex);
1426 atomic_set(&rdev->ih.lock, 0);
1427 mutex_init(&rdev->gem.mutex);
1428 mutex_init(&rdev->pm.mutex);
1429 mutex_init(&rdev->gpu_clock_mutex);
1430 mutex_init(&rdev->srbm_mutex);
1431 init_rwsem(&rdev->pm.mclk_lock);
1432 init_rwsem(&rdev->exclusive_lock);
1433 spin_lock_init(&rdev->irq.vblank_lock);
1434 DRM_INIT_WAITQUEUE(&rdev->irq.vblank_queue, "radvblnk");
1435 r = radeon_gem_init(rdev);
1439 radeon_check_arguments(rdev);
1443 rdev->vm_manager.max_pfn = radeon_vm_size << 18;
1446 r = radeon_asic_init(rdev);
1453 if ((rdev->family >= CHIP_RS400) &&
1454 (rdev->flags & RADEON_IS_IGP)) {
1455 rdev->flags &= ~RADEON_IS_AGP;
1458 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1459 radeon_agp_disable(rdev);
1466 if (rdev->family >= CHIP_CAYMAN)
1467 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1468 else if (rdev->family >= CHIP_CEDAR)
1469 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1471 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1480 if (rdev->flags & RADEON_IS_AGP)
1482 if ((rdev->flags & RADEON_IS_PCI) &&
1483 (rdev->family <= CHIP_RS740))
1486 if (rdev->family == CHIP_CEDAR)
1491 r = drm_limit_dma_space(rdev->ddev, 0, __BITS(dma_bits - 1, 0));
1493 r = dma_set_mask_and_coherent(&rdev->pdev->dev, DMA_BIT_MASK(dma_bits));
1499 rdev->need_swiotlb = drm_need_swiotlb(dma_bits);
1504 spin_lock_init(&rdev->mmio_idx_lock);
1505 spin_lock_init(&rdev->smc_idx_lock);
1506 spin_lock_init(&rdev->pll_idx_lock);
1507 spin_lock_init(&rdev->mc_idx_lock);
1508 spin_lock_init(&rdev->pcie_idx_lock);
1509 spin_lock_init(&rdev->pciep_idx_lock);
1510 spin_lock_init(&rdev->pif_idx_lock);
1511 spin_lock_init(&rdev->cg_idx_lock);
1512 spin_lock_init(&rdev->uvd_idx_lock);
1513 spin_lock_init(&rdev->rcu_idx_lock);
1514 spin_lock_init(&rdev->didt_idx_lock);
1515 spin_lock_init(&rdev->end_idx_lock);
1520 if (rdev->family >= CHIP_BONAIRE)
1524 if (pci_mapreg_map(&rdev->pdev->pd_pa, PCI_BAR(bar),
1525 pci_mapreg_type(rdev->pdev->pd_pa.pa_pc,
1526 rdev->pdev->pd_pa.pa_tag, PCI_BAR(bar)),
1528 &rdev->rmmio_bst, &rdev->rmmio_bsh,
1529 &rdev->rmmio_addr, &rdev->rmmio_size))
1533 (uintmax_t)rdev->rmmio_addr);
1535 (uintmax_t)rdev->rmmio_size);
1537 if (rdev->family >= CHIP_BONAIRE) {
1538 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1539 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1541 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1542 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1544 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1545 if (rdev->rmmio == NULL)
1550 if (rdev->family >= CHIP_BONAIRE)
1551 radeon_doorbell_init(rdev);
1556 if (pci_mapreg_map(&rdev->pdev->pd_pa, PCI_BAR(i),
1558 &rdev->rio_mem_bst, &rdev->rio_mem_bsh,
1559 NULL, &rdev->rio_mem_size))
1563 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1564 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1565 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1574 if (rdev->rio_mem == NULL)
1578 if (rdev->flags & RADEON_IS_PX)
1579 radeon_device_handle_px_quirks(rdev);
1585 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1587 if (rdev->flags & RADEON_IS_PX)
1589 if (!pci_is_thunderbolt_attached(rdev->pdev))
1590 vga_switcheroo_register_client(rdev->pdev,
1593 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1596 r = radeon_init(rdev);
1600 r = radeon_gem_debugfs_init(rdev);
1605 r = radeon_mst_debugfs_init(rdev);
1610 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1614 radeon_asic_reset(rdev);
1615 radeon_fini(rdev);
1616 radeon_agp_disable(rdev);
1617 r = radeon_init(rdev);
1622 r = radeon_ib_ring_tests(rdev);
1631 if (rdev->pm.dpm_enabled &&
1632 (rdev->pm.pm_method == PM_METHOD_DPM) &&
1633 (rdev->family == CHIP_TURKS) &&
1634 (rdev->flags & RADEON_IS_MOBILITY)) {
1635 mutex_lock(&rdev->pm.mutex);
1636 radeon_dpm_disable(rdev);
1637 radeon_dpm_enable(rdev);
1638 mutex_unlock(&rdev->pm.mutex);
1642 if (rdev->accel_working)
1643 radeon_test_moves(rdev);
1648 if (rdev->accel_working)
1649 radeon_test_syncing(rdev);
1654 if (rdev->accel_working)
1655 radeon_benchmark(rdev, radeon_benchmarking);
1664 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1672 * @rdev: radeon_device pointer
1677 void radeon_device_fini(struct radeon_device *rdev)
1680 rdev->shutdown = true;
1682 radeon_bo_evict_vram(rdev);
1683 radeon_fini(rdev);
1685 if (!pci_is_thunderbolt_attached(rdev->pdev))
1686 vga_switcheroo_unregister_client(rdev->pdev);
1687 if (rdev->flags & RADEON_IS_PX)
1688 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1689 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1692 if (rdev->rio_mem_size)
1693 bus_space_unmap(rdev->rio_mem_bst, rdev->rio_mem_bsh,
1694 rdev->rio_mem_size);
1695 rdev->rio_mem_size = 0;
1696 bus_space_unmap(rdev->rmmio_bst, rdev->rmmio_bsh, rdev->rmmio_size);
1698 if (rdev->rio_mem)
1699 pci_iounmap(rdev->pdev, rdev->rio_mem);
1700 rdev->rio_mem = NULL;
1701 iounmap(rdev->rmmio);
1702 rdev->rmmio = NULL;
1704 if (rdev->family >= CHIP_BONAIRE)
1705 radeon_doorbell_fini(rdev);
1707 DRM_DESTROY_WAITQUEUE(&rdev->irq.vblank_queue);
1708 spin_lock_destroy(&rdev->irq.vblank_lock);
1709 destroy_rwsem(&rdev->exclusive_lock);
1710 destroy_rwsem(&rdev->pm.mclk_lock);
1711 mutex_destroy(&rdev->srbm_mutex);
1712 mutex_destroy(&rdev->gpu_clock_mutex);
1713 mutex_destroy(&rdev->pm.mutex);
1714 mutex_destroy(&rdev->gem.mutex);
1715 mutex_destroy(&rdev->dc_hw_i2c_mutex);
1716 mutex_destroy(&rdev->ring_lock);
1736 struct radeon_device *rdev;
1745 rdev = dev->dev_private;
1779 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1788 radeon_bo_evict_vram(rdev);
1792 r = radeon_fence_wait_empty(rdev, i);
1795 radeon_fence_driver_force_completion(rdev, i);
1799 radeon_save_bios_scratch_regs(rdev);
1801 radeon_suspend(rdev);
1802 radeon_hpd_fini(rdev);
1807 radeon_bo_evict_vram(rdev);
1809 radeon_agp_suspend(rdev);
1813 if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) {
1814 rdev->asic->asic_reset(rdev, true);
1825 radeon_fbdev_set_suspend(rdev, 1);
1843 struct radeon_device *rdev = dev->dev_private;
1865 radeon_agp_resume(rdev);
1866 radeon_resume(rdev);
1868 r = radeon_ib_ring_tests(rdev);
1872 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1874 r = radeon_pm_late_init(rdev);
1876 rdev->pm.dpm_enabled = false;
1881 radeon_pm_resume(rdev);
1884 radeon_restore_bios_scratch_regs(rdev);
1897 ASIC_IS_AVIVO(rdev) ?
1908 if (rdev->is_atom_bios) {
1909 radeon_atom_encoder_init(rdev);
1910 radeon_atom_disp_eng_pll_init(rdev);
1912 if (rdev->mode_info.bl_encoder) {
1913 u8 bl_level = radeon_get_backlight_level(rdev,
1914 rdev->mode_info.bl_encoder);
1915 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1920 radeon_hpd_init(rdev);
1935 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1936 radeon_pm_compute_clocks(rdev);
1939 radeon_fbdev_set_suspend(rdev, 0);
1949 * @rdev: radeon device pointer
1954 int radeon_gpu_reset(struct radeon_device *rdev)
1964 down_write(&rdev->exclusive_lock);
1966 if (!rdev->needs_reset) {
1967 up_write(&rdev->exclusive_lock);
1971 atomic_inc(&rdev->gpu_reset_counter);
1973 radeon_save_bios_scratch_regs(rdev);
1975 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1976 radeon_suspend(rdev);
1977 radeon_hpd_fini(rdev);
1980 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1984 dev_info(rdev->dev, "Saved %d dwords of commands "
1989 r = radeon_asic_reset(rdev);
1991 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1992 radeon_resume(rdev);
1995 radeon_restore_bios_scratch_regs(rdev);
1999 radeon_ring_restore(rdev, &rdev->ring[i],
2002 radeon_fence_driver_force_completion(rdev, i);
2007 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2009 r = radeon_pm_late_init(rdev);
2011 rdev->pm.dpm_enabled = false;
2016 radeon_pm_resume(rdev);
2020 if (rdev->is_atom_bios) {
2021 radeon_atom_encoder_init(rdev);
2022 radeon_atom_disp_eng_pll_init(rdev);
2024 if (rdev->mode_info.bl_encoder) {
2025 u8 bl_level = radeon_get_backlight_level(rdev,
2026 rdev->mode_info.bl_encoder);
2027 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
2032 radeon_hpd_init(rdev);
2034 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
2036 rdev->in_reset = true;
2037 rdev->needs_reset = false;
2039 downgrade_write(&rdev->exclusive_lock);
2041 drm_helper_resume_force_mode(rdev->ddev);
2044 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
2045 radeon_pm_compute_clocks(rdev);
2048 r = radeon_ib_ring_tests(rdev);
2053 dev_info(rdev->dev, "GPU reset failed\n");
2056 rdev->needs_reset = r == -EAGAIN;
2057 rdev->in_reset = false;
2059 up_read(&rdev->exclusive_lock);
2067 int radeon_debugfs_add_files(struct radeon_device *rdev,
2073 for (i = 0; i < rdev->debugfs_count; i++) {
2074 if (rdev->debugfs[i].files == files) {
2080 i = rdev->debugfs_count + 1;
2087 rdev->debugfs[rdev->debugfs_count].files = files;
2088 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
2089 rdev->debugfs_count = i;
2092 rdev->ddev->primary->debugfs_root,
2093 rdev->ddev->primary);