Lines Matching refs:pll
941 * radeon_compute_pll_avivo - compute PLL paramaters
943 * @pll: information about the PLL
950 * Try to calculate the PLL parameters to generate the given frequency:
953 void radeon_compute_pll_avivo(struct radeon_pll *pll,
961 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
971 fb_div_min = pll->min_feedback_div;
972 fb_div_max = pll->max_feedback_div;
974 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
980 if (pll->flags & RADEON_PLL_USE_REF_DIV)
981 ref_div_min = pll->reference_div;
983 ref_div_min = pll->min_ref_div;
985 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
986 pll->flags & RADEON_PLL_USE_REF_DIV)
987 ref_div_max = pll->reference_div;
988 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
990 ref_div_max = min(pll->max_ref_div, 7u);
992 ref_div_max = pll->max_ref_div;
995 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
996 post_div_min = pll->post_div;
997 post_div_max = pll->post_div;
1001 if (pll->flags & RADEON_PLL_IS_LCD) {
1002 vco_min = pll->lcd_pll_out_min;
1003 vco_max = pll->lcd_pll_out_max;
1005 vco_min = pll->pll_out_min;
1006 vco_max = pll->pll_out_max;
1009 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1017 if (post_div_min < pll->min_post_div)
1018 post_div_min = pll->min_post_div;
1023 if (post_div_max > pll->max_post_div)
1024 post_div_max = pll->max_post_div;
1029 den = pll->reference_freq;
1035 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1045 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1049 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1066 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1076 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1084 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1085 (pll->reference_freq * *frac_fb_div_p)) /
1090 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1106 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1114 uint32_t min_ref_div = pll->min_ref_div;
1115 uint32_t max_ref_div = pll->max_ref_div;
1116 uint32_t min_post_div = pll->min_post_div;
1117 uint32_t max_post_div = pll->max_post_div;
1120 uint32_t best_vco = pll->best_vco;
1131 DRM_DEBUG_KMS("PLL freq %"PRIu64" %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1134 if (pll->flags & RADEON_PLL_IS_LCD) {
1135 pll_out_min = pll->lcd_pll_out_min;
1136 pll_out_max = pll->lcd_pll_out_max;
1138 pll_out_min = pll->pll_out_min;
1139 pll_out_max = pll->pll_out_max;
1145 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1146 min_ref_div = max_ref_div = pll->reference_div;
1150 uint32_t pll_in = pll->reference_freq / mid;
1151 if (pll_in < pll->pll_in_min)
1153 else if (pll_in > pll->pll_in_max)
1160 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1161 min_post_div = max_post_div = pll->post_div;
1163 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1164 min_fractional_feed_div = pll->min_frac_feedback_div;
1165 max_fractional_feed_div = pll->max_frac_feedback_div;
1171 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1175 if (pll->flags & RADEON_PLL_LEGACY) {
1189 uint32_t pll_in = pll->reference_freq / ref_div;
1190 uint32_t min_feed_div = pll->min_feedback_div;
1191 uint32_t max_feed_div = pll->max_feedback_div + 1;
1193 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1205 tmp = (uint64_t)pll->reference_freq * feedback_div;
1218 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1219 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1222 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1251 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1252 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1253 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1254 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1255 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1256 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1284 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1629 /* init dig PHYs, disp eng pll */
Indexes created Wed Oct 22 00:09:40 GMT 2025