Lines Matching refs:rlc
4032 /* halt the rlc */
4110 * RLC
4120 if (rdev->rlc.save_restore_obj) {
4121 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
4123 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
4124 radeon_bo_unpin(rdev->rlc.save_restore_obj);
4125 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
4127 radeon_bo_unref(&rdev->rlc.save_restore_obj);
4128 rdev->rlc.save_restore_obj = NULL;
4132 if (rdev->rlc.clear_state_obj) {
4133 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
4135 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
4136 radeon_bo_unpin(rdev->rlc.clear_state_obj);
4137 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
4139 radeon_bo_unref(&rdev->rlc.clear_state_obj);
4140 rdev->rlc.clear_state_obj = NULL;
4144 if (rdev->rlc.cp_table_obj) {
4145 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);
4147 dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r);
4148 radeon_bo_unpin(rdev->rlc.cp_table_obj);
4149 radeon_bo_unreserve(rdev->rlc.cp_table_obj);
4151 radeon_bo_unref(&rdev->rlc.cp_table_obj);
4152 rdev->rlc.cp_table_obj = NULL;
4168 src_ptr = rdev->rlc.reg_list;
4169 dws = rdev->rlc.reg_list_size;
4173 cs_data = rdev->rlc.cs_data;
4177 if (rdev->rlc.save_restore_obj == NULL) {
4180 NULL, &rdev->rlc.save_restore_obj);
4182 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
4187 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
4192 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
4193 &rdev->rlc.save_restore_gpu_addr);
4195 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
4196 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
4201 r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)__UNVOLATILE(&rdev->rlc.sr_ptr));
4203 dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r);
4208 dst_ptr = rdev->rlc.sr_ptr;
4211 for (i = 0; i < rdev->rlc.reg_list_size; i++)
4231 radeon_bo_kunmap(rdev->rlc.save_restore_obj);
4232 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
4238 rdev->rlc.clear_state_size = dws = cik_get_csb_size(rdev);
4240 rdev->rlc.clear_state_size = si_get_csb_size(rdev);
4241 dws = rdev->rlc.clear_state_size + (256 / 4);
4253 rdev->rlc.clear_state_size = dws;
4256 if (rdev->rlc.clear_state_obj == NULL) {
4259 NULL, &rdev->rlc.clear_state_obj);
4261 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
4266 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
4271 r = radeon_bo_pin(rdev->rlc
4272 &rdev->rlc.clear_state_gpu_addr);
4274 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
4275 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
4280 r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)__UNVOLATILE(&rdev->rlc.cs_ptr));
4282 dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r);
4287 dst_ptr = rdev->rlc.cs_ptr;
4291 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256;
4294 dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size);
4298 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);
4327 radeon_bo_kunmap(rdev->rlc.clear_state_obj);
4328 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
4331 if (rdev->rlc.cp_table_size) {
4332 if (rdev->rlc.cp_table_obj == NULL) {
4333 r = radeon_bo_create(rdev, rdev->rlc.cp_table_size,
4336 NULL, &rdev->rlc.cp_table_obj);
4338 dev_warn(rdev->dev, "(%d) create RLC cp table bo failed\n", r);
4344 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);
4346 dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r);
4350 r = radeon_bo_pin(rdev->rlc.cp_table_obj, RADEON_GEM_DOMAIN_VRAM,
4351 &rdev->rlc.cp_table_gpu_addr);
4353 radeon_bo_unreserve(rdev->rlc.cp_table_obj);
4354 dev_warn(rdev->dev, "(%d) pin RLC cp_table bo failed\n", r);
4358 r = radeon_bo_kmap(rdev->rlc.cp_table_obj, (void **)__UNVOLATILE(&rdev->rlc.cp_table_ptr));
4360 dev_warn(rdev->dev, "(%d) map RLC cp table bo failed\n", r);
4367 radeon_bo_kunmap(rdev->rlc.cp_table_obj);
4368 radeon_bo_unreserve(rdev->rlc.cp_table_obj);
4417 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
4418 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5045 /* allocate rlc buffers */
5047 rdev->rlc.reg_list = sumo_rlc_save_restore_register_list;
5048 rdev->rlc.reg_list_size =
5050 rdev->rlc.cs_data = evergreen_cs_data;
5053 DRM_ERROR("Failed to init rlc BOs!\n");
Indexes created Sat Oct 18 08:10:09 GMT 2025