Lines Matching refs:seq
70 * @seq: sequence number to write
75 static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
80 *drv->cpu_addr = cpu_to_le32(seq);
83 WREG32(drv->scratch_reg, seq);
99 u32 seq = 0;
103 seq = le32_to_cpu(*drv->cpu_addr);
105 seq = lower_32_bits(atomic64_read(&drv->last_seq));
108 seq = RREG32(drv->scratch_reg);
110 return seq;
146 u64 seq;
154 (*fence)->seq = seq = ++rdev->fence_drv[ring].sync_seq[ring];
160 seq);
162 trace_radeon_fence_emit(rdev->ddev, ring, (*fence)->seq);
176 u64 seq;
184 seq = atomic64_read(&fence->rdev->fence_drv[fence->ring].last_seq);
185 if (seq >= fence->seq) {
225 uint64_t seq, last_seq, last_emitted;
242 * value the other process set as last seq must be higher than
243 * the seq value we just read. Which means that current process
250 * seq but to an older one.
255 seq = radeon_fence_read(rdev, ring);
256 seq |= last_seq & 0xffffffff00000000LL;
257 if (seq < last_seq) {
258 seq &= 0xffffffff;
259 seq |= last_emitted & 0xffffffff00000000LL;
262 if (seq <= last_seq || seq > last_emitted) {
267 * seq we just read is different from the previous on.
270 last_seq = seq;
274 * seq then the current real last seq as signaled
279 } while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
281 if (seq < last_emitted)
370 * @seq: sequence number
381 u64 seq, unsigned ring)
384 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
389 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
400 u64 seq = fence->seq;
404 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
412 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
434 if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq)
444 if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq) {
479 if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) {
496 * @seq: sequence numbers
503 static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
510 if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i))
604 uint64_t seq[RADEON_NUM_RINGS] = {};
617 seq[fence->ring] = fence->seq;
618 r = radeon_fence_wait_seq_timeout(fence->rdev, seq, intr, timeout);
667 uint64_t seq[RADEON_NUM_RINGS];
672 seq[i] = 0;
678 seq[i] = fences[i]->seq;
686 r = radeon_fence_wait_seq_timeout(rdev, seq, intr, MAX_SCHEDULE_TIMEOUT);
705 uint64_t seq[RADEON_NUM_RINGS] = {};
708 seq[ring] = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
709 if (seq[ring] >= rdev->fence_drv[ring].sync_seq[ring]) {
714 r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
732 uint64_t seq[RADEON_NUM_RINGS] = {};
735 seq[ring] = rdev->fence_drv[ring].sync_seq[ring];
736 if (!seq[ring])
739 r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
833 if (fence->seq <= fdrv->sync_seq[fence->ring]) {
Indexes created Sun Oct 12 02:09:55 GMT 2025