Lines Matching refs:WREG32
127 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
130 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
141 WREG32(rec->mask_clk_reg, temp);
146 WREG32(rec->a_clk_reg, temp);
149 WREG32(rec->a_data_reg, temp);
153 WREG32(rec->en_clk_reg, temp);
156 WREG32(rec->en_data_reg, temp);
160 WREG32(rec->mask_clk_reg, temp);
164 WREG32(rec->mask_data_reg, temp);
179 WREG32(rec->mask_clk_reg, temp);
183 WREG32(rec->mask_data_reg, temp);
228 WREG32(rec->en_clk_reg, val);
241 WREG32(rec->en_data_reg, val);
362 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
476 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
480 WREG32(i2c_data, (p->addr << 1) & 0xff);
481 WREG32(i2c_data, 0);
482 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
486 WREG32(i2c_cntl_0, reg);
497 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
509 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
513 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
514 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
518 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
529 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
536 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
540 WREG32(i2c_data, (p->addr << 1) & 0xff);
541 WREG32(i2c_data, p->buf[j]);
542 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
546 WREG32(i2c_cntl_0, reg);
557 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
567 WREG32(i2c_cntl_0, 0);
568 WREG32(i2c_cntl_1, 0);
569 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
577 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
610 WREG32(rec->mask_clk_reg, tmp);
615 WREG32(rec->mask_data_reg, tmp);
621 WREG32(rec->a_clk_reg, tmp);
626 WREG32(rec->a_data_reg, tmp);
632 WREG32(rec->en_clk_reg, tmp);
637 WREG32(rec->en_data_reg, tmp);
642 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
645 WREG32(0x494, saved2 | 0x1);
647 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
679 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
682 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
684 WREG32(AVIVO_DC_I2C_RESET, 0);
686 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
687 WREG32(AVIVO_DC_I2C_DATA, 0);
689 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
690 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
693 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
694 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
705 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
723 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
726 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
728 WREG32(AVIVO_DC_I2C_RESET, 0);
730 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
731 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
732 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
735 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
736 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
747 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
763 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
766 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
768 WREG32(AVIVO_DC_I2C_RESET, 0);
770 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
772 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
774 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
775 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
778 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
779 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
790 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
802 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
805 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
807 WREG32(AVIVO_DC_I2C_RESET, 0);
809 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
810 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
811 WREG32(0x494, saved2);
814 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
Indexes created Wed Oct 22 13:09:56 GMT 2025