Lines Matching defs:rdev
67 struct radeon_device *rdev = dev->dev_private;
69 if (rdev == NULL)
74 if (rdev->rmmio_size)
77 if (rdev->rmmio == NULL)
86 radeon_acpi_fini(rdev);
88 radeon_modeset_fini(rdev);
89 radeon_device_fini(rdev);
92 kfree(rdev);
111 struct radeon_device *rdev;
114 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
115 if (rdev == NULL) {
118 dev->dev_private = (void *)rdev;
141 r = radeon_device_init(rdev, dev, dev->pdev, flags);
151 r = radeon_modeset_init(rdev);
159 acpi_status = radeon_acpi_init(rdev);
198 struct radeon_device *rdev = dev->dev_private;
200 mutex_lock(&rdev->gem.mutex);
211 mutex_unlock(&rdev->gem.mutex);
220 * @rdev: radeon device pointer
231 struct radeon_device *rdev = dev->dev_private;
233 struct radeon_mode_info *minfo = &rdev->mode_info;
248 *value = rdev->num_gb_pipes;
251 *value = rdev->num_z_pipes;
255 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
258 *value = rdev->accel_working;
265 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
280 if (rdev->family == CHIP_HAWAII) {
281 if (rdev->accel_working) {
282 if (rdev->new_fw)
290 *value = rdev->accel_working;
294 if (rdev->family >= CHIP_BONAIRE)
295 *value = rdev->config.cik.tile_config;
296 else if (rdev->family >= CHIP_TAHITI)
297 *value = rdev->config.si.tile_config;
298 else if (rdev->family >= CHIP_CAYMAN)
299 *value = rdev->config.cayman.tile_config;
300 else if (rdev->family >= CHIP_CEDAR)
301 *value = rdev->config.evergreen.tile_config;
302 else if (rdev->family >= CHIP_RV770)
303 *value = rdev->config.rv770.tile_config;
304 else if (rdev->family >= CHIP_R600)
305 *value = rdev->config.r600.tile_config;
326 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
338 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
342 if (rdev->asic->get_xclk)
343 *value = radeon_get_xclk(rdev) * 10;
345 *value = rdev->clock.spll.reference_freq * 10;
348 if (rdev->family >= CHIP_BONAIRE)
349 *value = rdev->config.cik.max_backends_per_se *
350 rdev->config.cik.max_shader_engines;
351 else if (rdev->family >= CHIP_TAHITI)
352 *value = rdev->config.si.max_backends_per_se *
353 rdev->config.si.max_shader_engines;
354 else if (rdev->family >= CHIP_CAYMAN)
355 *value = rdev->config.cayman.max_backends_per_se *
356 rdev->config.cayman.max_shader_engines;
357 else if (rdev->family >= CHIP_CEDAR)
358 *value = rdev->config.evergreen.max_backends;
359 else if (rdev->family >= CHIP_RV770)
360 *value = rdev->config.rv770.max_backends;
361 else if (rdev->family >= CHIP_R600)
362 *value = rdev->config.r600.max_backends;
368 if (rdev->family >= CHIP_BONAIRE)
369 *value = rdev->config.cik.max_tile_pipes;
370 else if (rdev->family >= CHIP_TAHITI)
371 *value = rdev->config.si.max_tile_pipes;
372 else if (rdev->family >= CHIP_CAYMAN)
373 *value = rdev->config.cayman.max_tile_pipes;
374 else if (rdev->family >= CHIP_CEDAR)
375 *value = rdev->config.evergreen.max_tile_pipes;
376 else if (rdev->family >= CHIP_RV770)
377 *value = rdev->config.rv770.max_tile_pipes;
378 else if (rdev->family >= CHIP_R600)
379 *value = rdev->config.r600.max_tile_pipes;
388 if (rdev->family >= CHIP_BONAIRE)
389 *value = rdev->config.cik.backend_map;
390 else if (rdev->family >= CHIP_TAHITI)
391 *value = rdev->config.si.backend_map;
392 else if (rdev->family >= CHIP_CAYMAN)
393 *value = rdev->config.cayman.backend_map;
394 else if (rdev->family >= CHIP_CEDAR)
395 *value = rdev->config.evergreen.backend_map;
396 else if (rdev->family >= CHIP_RV770)
397 *value = rdev->config.rv770.backend_map;
398 else if (rdev->family >= CHIP_R600)
399 *value = rdev->config.r600.backend_map;
406 if (rdev->family < CHIP_CAYMAN)
412 if (rdev->family < CHIP_CAYMAN)
417 if (rdev->family >= CHIP_BONAIRE)
418 *value = rdev->config.cik.max_cu_per_sh;
419 else if (rdev->family >= CHIP_TAHITI)
420 *value = rdev->config.si.max_cu_per_sh;
421 else if (rdev->family >= CHIP_CAYMAN)
422 *value = rdev->config.cayman.max_pipes_per_simd;
423 else if (rdev->family >= CHIP_CEDAR)
424 *value = rdev->config.evergreen.max_pipes;
425 else if (rdev->family >= CHIP_RV770)
426 *value = rdev->config.rv770.max_pipes;
427 else if (rdev->family >= CHIP_R600)
428 *value = rdev->config.r600.max_pipes;
434 if (rdev->family < CHIP_R600) {
440 value64 = radeon_get_gpu_clock_counter(rdev);
443 if (rdev->family >= CHIP_BONAIRE)
444 *value = rdev->config.cik.max_shader_engines;
445 else if (rdev->family >= CHIP_TAHITI)
446 *value = rdev->config.si.max_shader_engines;
447 else if (rdev->family >= CHIP_CAYMAN)
448 *value = rdev->config.cayman.max_shader_engines;
449 else if (rdev->family >= CHIP_CEDAR)
450 *value = rdev->config.evergreen.num_ses;
455 if (rdev->family >= CHIP_BONAIRE)
456 *value = rdev->config.cik.max_sh_per_se;
457 else if (rdev->family >= CHIP_TAHITI)
458 *value = rdev->config.si.max_sh_per_se;
463 *value = rdev->fastfb_working;
473 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
476 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
477 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
480 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
483 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
490 if (rdev->family >= CHIP_BONAIRE) {
491 value = rdev->config.cik.tile_mode_array;
493 } else if (rdev->family >= CHIP_TAHITI) {
494 value = rdev->config.si.tile_mode_array;
502 if (rdev->family >= CHIP_BONAIRE) {
503 value = rdev->config.cik.macrotile_mode_array;
514 if (rdev->family >= CHIP_BONAIRE) {
515 *value = rdev->config.cik.backend_enable_mask;
516 } else if (rdev->family >= CHIP_TAHITI) {
517 *value = rdev->config.si.backend_enable_mask;
523 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
524 rdev->pm.dpm_enabled)
525 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
527 *value = rdev->pm.default_sclk * 10;
530 *value = rdev->vce.fw_version;
533 *value = rdev->vce.fb_version;
538 value64 = atomic64_read(&rdev->num_bytes_moved);
543 value64 = atomic64_read(&rdev->vram_usage);
548 value64 = atomic64_read(&rdev->gtt_usage);
551 if (rdev->family >= CHIP_BONAIRE)
552 *value = rdev->config.cik.active_cus;
553 else if (rdev->family >= CHIP_TAHITI)
554 *value = rdev->config.si.active_cus;
555 else if (rdev->family >= CHIP_CAYMAN)
556 *value = rdev->config.cayman.active_simds;
557 else if (rdev->family >= CHIP_CEDAR)
558 rdev->config.evergreen.active_simds;
559 else if (rdev->family >= CHIP_RV770)
560 *value = rdev->config.rv770.active_simds;
561 else if (rdev->family >= CHIP_R600)
562 *value = rdev->config.r600.active_simds;
568 if (rdev->asic->pm.get_temperature)
569 *value = radeon_get_temperature(rdev);
575 if (rdev->pm.dpm_enabled)
576 *value = radeon_dpm_get_current_sclk(rdev) / 100;
578 *value = rdev->pm.current_sclk / 100;
582 if (rdev->pm.dpm_enabled)
583 *value = radeon_dpm_get_current_mclk(rdev) / 100;
585 *value = rdev->pm.current_mclk / 100;
592 if (radeon_get_allowed_info_register(rdev, *value, value))
599 *value = atomic_read(&rdev->gpu_reset_counter);
642 struct radeon_device *rdev = dev->dev_private;
652 if (rdev->family >= CHIP_CAYMAN) {
662 if (rdev->accel_working) {
664 r = radeon_vm_init(rdev, vm);
670 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
672 radeon_vm_fini(rdev, vm);
679 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
680 rdev->ring_tmp_bo.bo);
681 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
686 radeon_vm_fini(rdev, vm);
712 struct radeon_device *rdev = dev->dev_private;
716 mutex_lock(&rdev->gem.mutex);
717 if (rdev->hyperz_filp == file_priv)
718 rdev->hyperz_filp = NULL;
719 if (rdev->cmask_filp == file_priv)
720 rdev->cmask_filp = NULL;
721 mutex_unlock(&rdev->gem.mutex);
723 radeon_uvd_free_handles(rdev, file_priv);
724 radeon_vce_free_handles(rdev, file_priv);
727 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
732 if (rdev->accel_working) {
733 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
736 radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
737 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
739 radeon_vm_fini(rdev, vm);
765 struct radeon_device *rdev = dev->dev_private;
767 if (pipe >= rdev->num_crtc) {
780 if (rdev->mode_info.crtcs[pipe]) {
785 count = radeon_get_vblank_counter(rdev, pipe);
793 &rdev->mode_info.crtcs[pipe]->base.hwmode);
794 } while (count != radeon_get_vblank_counter(rdev, pipe));
814 count = radeon_get_vblank_counter(rdev, pipe);
832 struct radeon_device *rdev = dev->dev_private;
836 if (crtc < 0 || crtc >= rdev->num_crtc) {
841 spin_lock_irqsave(&rdev->irq.lock, irqflags);
842 rdev->irq.crtc_vblank_int[crtc] = true;
843 r = radeon_irq_set(rdev);
844 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
858 struct radeon_device *rdev = dev->dev_private;
861 if (crtc < 0 || crtc >= rdev->num_crtc) {
866 spin_lock_irqsave(&rdev->irq.lock, irqflags);
867 rdev->irq.crtc_vblank_int[crtc] = false;
868 radeon_irq_set(rdev);
869 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
Indexes created Sun Oct 12 09:09:55 GMT 2025