Lines Matching refs:rdev
55 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
56 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
57 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
58 static void radeon_pm_update_profile(struct radeon_device *rdev);
59 static void radeon_pm_set_clocks(struct radeon_device *rdev);
61 int radeon_pm_get_type_index(struct radeon_device *rdev,
68 for (i = 0; i < rdev->pm.num_power_states; i++) {
69 if (rdev->pm.power_state[i].type == ps_type) {
76 return rdev->pm.default_power_state_index;
79 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
81 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
82 mutex_lock(&rdev->pm.mutex);
84 rdev->pm.dpm.ac_power = true;
86 rdev->pm.dpm.ac_power = false;
87 if (rdev->family == CHIP_ARUBA) {
88 if (rdev->asic->dpm.enable_bapm)
89 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
91 mutex_unlock(&rdev->pm.mutex);
92 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
93 if (rdev->pm.profile == PM_PROFILE_AUTO) {
94 mutex_lock(&rdev->pm.mutex);
95 radeon_pm_update_profile(rdev);
96 radeon_pm_set_clocks(rdev);
97 mutex_unlock(&rdev->pm.mutex);
102 static void radeon_pm_update_profile(struct radeon_device *rdev)
104 switch (rdev->pm.profile) {
106 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
110 if (rdev->pm.active_crtc_count > 1)
111 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
113 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
115 if (rdev->pm.active_crtc_count > 1)
116 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
118 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
122 if (rdev->pm.active_crtc_count > 1)
123 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
125 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
128 if (rdev->pm.active_crtc_count > 1)
129 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
131 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
134 if (rdev->pm.active_crtc_count > 1)
135 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
137 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
141 if (rdev->pm.active_crtc_count == 0) {
142 rdev->pm.requested_power_state_index =
143 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
144 rdev->pm.requested_clock_mode_index =
145 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
147 rdev->pm.requested_power_state_index =
148 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
149 rdev->pm.requested_clock_mode_index =
150 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
154 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
158 if (list_empty(&rdev->gem.objects))
161 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
167 static void radeon_sync_with_vblank(struct radeon_device *rdev)
169 if (rdev->pm.active_crtcs) {
173 spin_lock(&rdev->irq.vblank_lock);
174 rdev->pm.vblank_sync = false;
175 DRM_SPIN_TIMED_WAIT_NOINTR_UNTIL(ret, &rdev->irq.vblank_queue,
176 &rdev->irq.vblank_lock,
178 rdev->pm.vblank_sync);
179 spin_unlock(&rdev->irq.vblank_lock);
181 rdev->pm.vblank_sync = false;
183 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
189 static void radeon_set_power_state(struct radeon_device *rdev)
194 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
195 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
198 if (radeon_gui_idle(rdev)) {
199 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
200 clock_info[rdev->pm.requested_clock_mode_index].sclk;
201 if (sclk > rdev->pm.default_sclk)
202 sclk = rdev->pm.default_sclk;
208 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
209 (rdev->family >= CHIP_BARTS) &&
210 rdev->pm.active_crtc_count &&
211 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
212 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
213 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
214 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
216 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
217 clock_info[rdev->pm.requested_clock_mode_index].mclk;
219 if (mclk > rdev->pm.default_mclk)
220 mclk = rdev->pm.default_mclk;
223 if (sclk < rdev->pm.current_sclk)
226 radeon_sync_with_vblank(rdev);
228 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
229 if (!radeon_pm_in_vbl(rdev))
233 radeon_pm_prepare(rdev);
237 radeon_pm_misc(rdev);
240 if (sclk != rdev->pm.current_sclk) {
241 radeon_pm_debug_check_in_vbl(rdev, false);
242 radeon_set_engine_clock(rdev, sclk);
243 radeon_pm_debug_check_in_vbl(rdev, true);
244 rdev->pm.current_sclk = sclk;
249 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
250 radeon_pm_debug_check_in_vbl(rdev, false);
251 radeon_set_memory_clock(rdev, mclk);
252 radeon_pm_debug_check_in_vbl(rdev, true);
253 rdev->pm.current_mclk = mclk;
259 radeon_pm_misc(rdev);
261 radeon_pm_finish(rdev);
263 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
264 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
269 static void radeon_pm_set_clocks(struct radeon_device *rdev)
275 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
276 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
279 down_write(&rdev->pm.mclk_lock);
280 mutex_lock(&rdev->ring_lock);
284 struct radeon_ring *ring = &rdev->ring[i];
288 r = radeon_fence_wait_empty(rdev, i);
291 mutex_unlock(&rdev->ring_lock);
292 up_write(&rdev->pm.mclk_lock);
297 radeon_unmap_vram_bos(rdev);
299 if (rdev->irq.installed) {
301 drm_for_each_crtc(crtc, rdev->ddev) {
302 if (rdev->pm.active_crtcs & (1 << i)) {
305 rdev->pm.req_vblank |= (1 << i);
314 radeon_set_power_state(rdev);
316 if (rdev->irq.installed) {
318 drm_for_each_crtc(crtc, rdev->ddev) {
319 if (rdev->pm.req_vblank & (1 << i)) {
320 rdev->pm.req_vblank &= ~(1 << i);
328 radeon_update_bandwidth_info(rdev);
329 if (rdev->pm.active_crtc_count)
330 radeon_bandwidth_update(rdev);
332 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
334 mutex_unlock(&rdev->ring_lock);
335 up_write(&rdev->pm.mclk_lock);
338 static void radeon_pm_print_states(struct radeon_device *rdev)
344 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
345 for (i = 0; i < rdev->pm.num_power_states; i++) {
346 power_state = &rdev->pm.power_state[i];
349 if (i == rdev->pm.default_power_state_index)
351 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
358 if (rdev->flags & RADEON_IS_IGP)
378 struct radeon_device *rdev = ddev->dev_private;
379 int cp = rdev->pm.profile;
394 struct radeon_device *rdev = ddev->dev_private;
397 if ((rdev->flags & RADEON_IS_PX) &&
401 mutex_lock(&rdev->pm.mutex);
402 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
404 rdev->pm.profile = PM_PROFILE_DEFAULT;
406 rdev->pm.profile = PM_PROFILE_AUTO;
408 rdev->pm.profile = PM_PROFILE_LOW;
410 rdev->pm.profile = PM_PROFILE_MID;
412 rdev->pm.profile = PM_PROFILE_HIGH;
417 radeon_pm_update_profile(rdev);
418 radeon_pm_set_clocks(rdev);
423 mutex_unlock(&rdev->pm.mutex);
433 struct radeon_device *rdev = ddev->dev_private;
434 int pm = rdev->pm.pm_method;
447 struct radeon_device *rdev = ddev->dev_private;
450 if ((rdev->flags & RADEON_IS_PX) &&
457 if (rdev->pm.pm_method == PM_METHOD_DPM) {
463 mutex_lock(&rdev->pm.mutex);
464 rdev->pm.pm_method = PM_METHOD_DYNPM;
465 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
466 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
467 mutex_unlock(&rdev->pm.mutex);
469 mutex_lock(&rdev->pm.mutex);
471 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
472 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
473 rdev->pm.pm_method = PM_METHOD_PROFILE;
474 mutex_unlock(&rdev->pm.mutex);
475 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
480 radeon_pm_compute_clocks(rdev);
490 struct radeon_device *rdev = ddev->dev_private;
491 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
504 struct radeon_device *rdev = ddev->dev_private;
506 mutex_lock(&rdev->pm.mutex);
508 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
510 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
512 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
514 mutex_unlock(&rdev->pm.mutex);
518 mutex_unlock(&rdev->pm.mutex);
521 if (!(rdev->flags & RADEON_IS_PX) ||
523 radeon_pm_compute_clocks(rdev);
534 struct radeon_device *rdev = ddev->dev_private;
535 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
537 if ((rdev->flags & RADEON_IS_PX) &&
552 struct radeon_device *rdev = ddev->dev_private;
557 if ((rdev->flags & RADEON_IS_PX) &&
561 mutex_lock(&rdev->pm.mutex);
572 if (rdev->asic->dpm.force_performance_level) {
573 if (rdev->pm.dpm.thermal_active) {
577 ret = radeon_dpm_force_performance_level(rdev, level);
582 mutex_unlock(&rdev->pm.mutex);
591 struct radeon_device *rdev = dev_get_drvdata(dev);
594 if (rdev->asic->dpm.fan_ctrl_get_mode)
595 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev);
606 struct radeon_device *rdev = dev_get_drvdata(dev);
610 if(!rdev->asic->dpm.fan_ctrl_set_mode)
619 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC);
622 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0);
647 struct radeon_device *rdev = dev_get_drvdata(dev);
657 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value);
668 struct radeon_device *rdev = dev_get_drvdata(dev);
672 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed);
694 struct radeon_device *rdev = dev_get_drvdata(dev);
695 struct drm_device *ddev = rdev->ddev;
699 if ((rdev->flags & RADEON_IS_PX) &&
703 if (rdev->asic->pm.get_temperature)
704 temp = radeon_get_temperature(rdev);
715 struct radeon_device *rdev = dev_get_drvdata(dev);
720 temp = rdev->pm.dpm.thermal.min_temp;
722 temp = rdev->pm.dpm.thermal.max_temp;
751 struct radeon_device *rdev = dev_get_drvdata(dev);
755 if (rdev->pm.pm_method != PM_METHOD_DPM &&
765 if (rdev->pm.no_fan &&
773 if ((!rdev->asic->dpm.get_fan_speed_percent &&
775 (!rdev->asic->dpm.fan_ctrl_get_mode &&
779 if ((!rdev->asic->dpm.set_fan_speed_percent &&
781 (!rdev->asic->dpm.fan_ctrl_set_mode &&
786 if ((!rdev->asic->dpm.set_fan_speed_percent &&
787 !rdev->asic->dpm.get_fan_speed_percent) &&
806 static int radeon_hwmon_init(struct radeon_device *rdev)
811 switch (rdev->pm.int_thermal_type) {
820 if (rdev->asic->pm.get_temperature == NULL)
822 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
823 "radeon", rdev,
825 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
826 err = PTR_ERR(rdev->pm.int_hwmon_dev);
827 dev_err(rdev->dev,
839 static void radeon_hwmon_fini(struct radeon_device *rdev)
842 if (rdev->pm.int_hwmon_dev)
843 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
849 struct radeon_device *rdev =
855 if (!rdev->pm.dpm_enabled)
858 if (rdev->asic->pm.get_temperature) {
859 int temp = radeon_get_temperature(rdev);
861 if (temp < rdev->pm.dpm.thermal.min_temp)
863 dpm_state = rdev->pm.dpm.user_state;
865 if (rdev->pm.dpm.thermal.high_to_low)
867 dpm_state = rdev->pm.dpm.user_state;
869 mutex_lock(&rdev->pm.mutex);
871 rdev->pm.dpm.thermal_active = true;
873 rdev->pm.dpm.thermal_active = false;
874 rdev->pm.dpm.state = dpm_state;
875 mutex_unlock(&rdev->pm.mutex);
877 radeon_pm_compute_clocks(rdev);
880 static bool radeon_dpm_single_display(struct radeon_device *rdev)
882 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
886 if (single_display && rdev->asic->dpm.vblank_too_short) {
887 if (radeon_dpm_vblank_too_short(rdev))
894 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
900 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
906 bool single_display = radeon_dpm_single_display(rdev);
919 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
920 ps = &rdev->pm.dpm.ps[i];
953 if (rdev->pm.dpm.uvd_ps)
954 return rdev->pm.dpm.uvd_ps;
974 return rdev->pm.dpm.boot_ps;
1003 if (rdev->pm.dpm.uvd_ps) {
1004 return rdev->pm.dpm.uvd_ps;
1027 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
1033 bool single_display = radeon_dpm_single_display(rdev);
1036 if (!rdev->pm.dpm_enabled)
1039 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
1041 if ((!rdev->pm.dpm.thermal_active) &&
1042 (!rdev->pm.dpm.uvd_active))
1043 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
1045 dpm_state = rdev->pm.dpm.state;
1047 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
1049 rdev->pm.dpm.requested_ps = ps;
1054 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
1056 if (ps->vce_active != rdev->pm.dpm.vce_active)
1059 if (rdev->pm.dpm.single_display != single_display)
1061 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
1065 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
1067 radeon_bandwidth_update(rdev);
1069 radeon_dpm_display_configuration_changed(rdev);
1070 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1071 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1079 if (rdev->pm.dpm.new_active_crtcs ==
1080 rdev->pm.dpm.current_active_crtcs) {
1083 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
1084 (rdev->pm.dpm.new_active_crtc_count > 1)) {
1086 radeon_bandwidth_update(rdev);
1088 radeon_dpm_display_configuration_changed(rdev);
1089 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1090 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1100 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
1102 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
1105 down_write(&rdev->pm.mclk_lock);
1106 mutex_lock(&rdev->ring_lock);
1109 ps->vce_active = rdev->pm.dpm.vce_active;
1111 ret = radeon_dpm_pre_set_power_state(rdev);
1116 radeon_bandwidth_update(rdev);
1118 radeon_dpm_display_configuration_changed(rdev);
1122 struct radeon_ring *ring = &rdev->ring[i];
1124 radeon_fence_wait_empty(rdev, i);
1128 radeon_dpm_set_power_state(rdev);
1131 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
1133 radeon_dpm_post_set_power_state(rdev);
1135 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1136 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1137 rdev->pm.dpm.single_display = single_display;
1139 if (rdev->asic->dpm.force_performance_level) {
1140 if (rdev->pm.dpm.thermal_active) {
1141 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1143 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
1145 rdev->pm.dpm.forced_level = level;
1148 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
1153 mutex_unlock(&rdev->ring_lock);
1154 up_write(&rdev->pm.mclk_lock);
1157 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
1161 if (rdev->asic->dpm.powergate_uvd) {
1162 mutex_lock(&rdev->pm.mutex);
1165 enable |= rdev->pm.dpm.sd > 0;
1166 enable |= rdev->pm.dpm.hd > 0;
1168 radeon_dpm_powergate_uvd(rdev, !enable);
1169 mutex_unlock(&rdev->pm.mutex);
1172 mutex_lock(&rdev->pm.mutex);
1173 rdev->pm.dpm.uvd_active = true;
1176 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
1178 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
1180 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
1182 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
1187 rdev->pm.dpm.state = dpm_state;
1188 mutex_unlock(&rdev->pm.mutex);
1190 mutex_lock(&rdev->pm.mutex);
1191 rdev->pm.dpm.uvd_active = false;
1192 mutex_unlock(&rdev->pm.mutex);
1195 radeon_pm_compute_clocks(rdev);
1199 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1202 mutex_lock(&rdev->pm.mutex);
1203 rdev->pm.dpm.vce_active = true;
1205 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1206 mutex_unlock(&rdev->pm.mutex);
1208 mutex_lock(&rdev->pm.mutex);
1209 rdev->pm.dpm.vce_active = false;
1210 mutex_unlock(&rdev->pm.mutex);
1213 radeon_pm_compute_clocks(rdev);
1216 static void radeon_pm_suspend_old(struct radeon_device *rdev)
1218 mutex_lock(&rdev->pm.mutex);
1219 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1220 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1221 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1223 mutex_unlock(&rdev->pm.mutex);
1225 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1228 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1230 mutex_lock(&rdev->pm.mutex);
1232 radeon_dpm_disable(rdev);
1234 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1235 rdev->pm.dpm_enabled = false;
1236 mutex_unlock(&rdev->pm.mutex);
1239 void radeon_pm_suspend(struct radeon_device *rdev)
1241 if (rdev->pm.pm_method == PM_METHOD_DPM)
1242 radeon_pm_suspend_dpm(rdev);
1244 radeon_pm_suspend_old(rdev);
1247 static void radeon_pm_resume_old(struct radeon_device *rdev)
1250 if ((rdev->family >= CHIP_BARTS) &&
1251 (rdev->family <= CHIP_CAYMAN) &&
1252 rdev->mc_fw) {
1253 if (rdev->pm.default_vddc)
1254 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1256 if (rdev->pm.default_vddci)
1257 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1259 if (rdev->pm.default_sclk)
1260 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1261 if (rdev->pm.default_mclk)
1262 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1265 mutex_lock(&rdev->pm.mutex);
1266 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1267 rdev->pm.current_clock_mode_index = 0;
1268 rdev->pm.current_sclk = rdev->pm.default_sclk;
1269 rdev->pm.current_mclk = rdev->pm.default_mclk;
1270 if (rdev->pm.power_state) {
1271 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1272 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1274 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1275 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1276 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1277 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1280 mutex_unlock(&rdev->pm.mutex);
1281 radeon_pm_compute_clocks(rdev);
1284 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1289 mutex_lock(&rdev->pm.mutex);
1290 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1291 radeon_dpm_setup_asic(rdev);
1292 ret = radeon_dpm_enable(rdev);
1293 mutex_unlock(&rdev->pm.mutex);
1296 rdev->pm.dpm_enabled = true;
1301 if ((rdev->family >= CHIP_BARTS) &&
1302 (rdev->family <= CHIP_CAYMAN) &&
1303 rdev->mc_fw) {
1304 if (rdev->pm.default_vddc)
1305 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1307 if (rdev->pm.default_vddci)
1308 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1310 if (rdev->pm.default_sclk)
1311 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1312 if (rdev->pm.default_mclk)
1313 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1317 void radeon_pm_resume(struct radeon_device *rdev)
1319 if (rdev->pm.pm_method == PM_METHOD_DPM)
1320 radeon_pm_resume_dpm(rdev);
1322 radeon_pm_resume_old(rdev);
1325 static int radeon_pm_init_old(struct radeon_device *rdev)
1329 rdev->pm.profile = PM_PROFILE_DEFAULT;
1330 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1331 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1332 rdev->pm.dynpm_can_upclock = true;
1333 rdev->pm.dynpm_can_downclock = true;
1334 rdev->pm.default_sclk = rdev->clock.default_sclk;
1335 rdev->pm.default_mclk = rdev->clock.default_mclk;
1336 rdev->pm.current_sclk = rdev->clock.default_sclk;
1337 rdev->pm.current_mclk = rdev->clock.default_mclk;
1338 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1340 if (rdev->bios) {
1341 if (rdev->is_atom_bios)
1342 radeon_atombios_get_power_modes(rdev);
1344 radeon_combios_get_power_modes(rdev);
1345 radeon_pm_print_states(rdev);
1346 radeon_pm_init_profile(rdev);
1348 if ((rdev->family >= CHIP_BARTS) &&
1349 (rdev->family <= CHIP_CAYMAN) &&
1350 rdev->mc_fw) {
1351 if (rdev->pm.default_vddc)
1352 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1354 if (rdev->pm.default_vddci)
1355 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1357 if (rdev->pm.default_sclk)
1358 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1359 if (rdev->pm.default_mclk)
1360 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1365 ret = radeon_hwmon_init(rdev);
1369 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1372 if (rdev->pm.num_power_states > 1) {
1373 if (radeon_debugfs_pm_init(rdev)) {
1384 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1388 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1390 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1394 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1399 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1400 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1401 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1402 rdev->pm.default_sclk = rdev->clock.default_sclk;
1403 rdev->pm.default_mclk = rdev->clock.default_mclk;
1404 rdev->pm.current_sclk = rdev->clock.default_sclk;
1405 rdev->pm.current_mclk = rdev->clock.default_mclk;
1406 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1408 if (rdev->bios && rdev->is_atom_bios)
1409 radeon_atombios_get_power_modes(rdev);
1414 ret = radeon_hwmon_init(rdev);
1418 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1419 mutex_lock(&rdev->pm.mutex);
1420 radeon_dpm_init(rdev);
1421 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1423 radeon_dpm_print_power_states(rdev);
1424 radeon_dpm_setup_asic(rdev);
1425 ret = radeon_dpm_enable(rdev);
1426 mutex_unlock(&rdev->pm.mutex);
1429 rdev->pm.dpm_enabled = true;
1431 if (radeon_debugfs_pm_init(rdev)) {
1440 rdev->pm.dpm_enabled = false;
1441 if ((rdev->family >= CHIP_BARTS) &&
1442 (rdev->family <= CHIP_CAYMAN) &&
1443 rdev->mc_fw) {
1444 if (rdev->pm.default_vddc)
1445 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1447 if (rdev->pm.default_vddci)
1448 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1450 if (rdev->pm.default_sclk)
1451 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1452 if (rdev->pm.default_mclk)
1453 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1475 int radeon_pm_init(struct radeon_device *rdev)
1482 if (rdev->pdev->vendor == p->chip_vendor &&
1483 rdev->pdev->device == p->chip_device &&
1484 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
1485 rdev->pdev->subsystem_device == p->subsys_device) {
1493 switch (rdev->family) {
1503 if (!rdev->rlc_fw)
1504 rdev->pm.pm_method = PM_METHOD_PROFILE;
1505 else if ((rdev->family >= CHIP_RV770) &&
1506 (!(rdev->flags & RADEON_IS_IGP)) &&
1507 (!rdev->smc_fw))
1508 rdev->pm.pm_method = PM_METHOD_PROFILE;
1510 rdev->pm.pm_method = PM_METHOD_DPM;
1512 rdev->pm.pm_method = PM_METHOD_PROFILE;
1541 if (!rdev->rlc_fw)
1542 rdev->pm.pm_method = PM_METHOD_PROFILE;
1543 else if ((rdev->family >= CHIP_RV770) &&
1544 (!(rdev->flags & RADEON_IS_IGP)) &&
1545 (!rdev->smc_fw))
1546 rdev->pm.pm_method = PM_METHOD_PROFILE;
1548 rdev->pm.pm_method = PM_METHOD_PROFILE;
1550 rdev->pm.pm_method = PM_METHOD_PROFILE;
1552 rdev->pm.pm_method = PM_METHOD_DPM;
1556 rdev->pm.pm_method = PM_METHOD_PROFILE;
1560 if (rdev->pm.pm_method == PM_METHOD_DPM)
1561 return radeon_pm_init_dpm(rdev);
1563 return radeon_pm_init_old(rdev);
1566 int radeon_pm_late_init(struct radeon_device *rdev)
1570 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1571 if (rdev->pm.dpm_enabled) {
1573 if (!rdev->pm.sysfs_initialized) {
1574 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1577 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1581 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1584 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1587 rdev->pm.sysfs_initialized = true;
1591 mutex_lock(&rdev->pm.mutex);
1592 ret = radeon_dpm_late_enable(rdev);
1593 mutex_unlock(&rdev->pm.mutex);
1595 rdev->pm.dpm_enabled = false;
1601 radeon_pm_compute_clocks(rdev);
1605 if ((rdev->pm.num_power_states > 1) &&
1606 (!rdev->pm.sysfs_initialized)) {
1609 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1612 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1616 rdev->pm.sysfs_initialized = true;
1623 static void radeon_pm_fini_old(struct radeon_device *rdev)
1625 if (rdev->pm.num_power_states > 1) {
1626 mutex_lock(&rdev->pm.mutex);
1627 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1628 rdev->pm.profile = PM_PROFILE_DEFAULT;
1629 radeon_pm_update_profile(rdev);
1630 radeon_pm_set_clocks(rdev);
1631 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1633 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1634 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1635 radeon_pm_set_clocks(rdev);
1637 mutex_unlock(&rdev->pm.mutex);
1639 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1642 device_remove_file(rdev->dev, &dev_attr_power_profile);
1643 device_remove_file(rdev->dev, &dev_attr_power_method);
1647 radeon_hwmon_fini(rdev);
1648 kfree(rdev->pm.power_state);
1651 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1653 if (rdev->pm.num_power_states > 1) {
1654 mutex_lock(&rdev->pm.mutex);
1655 radeon_dpm_disable(rdev);
1656 mutex_unlock(&rdev->pm.mutex);
1659 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1660 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1662 device_remove_file(rdev->dev, &dev_attr_power_profile);
1663 device_remove_file(rdev->dev, &dev_attr_power_method);
1666 radeon_dpm_fini(rdev);
1668 radeon_hwmon_fini(rdev);
1669 kfree(rdev->pm.power_state);
1672 void radeon_pm_fini(struct radeon_device *rdev)
1674 if (rdev->pm.pm_method == PM_METHOD_DPM)
1675 radeon_pm_fini_dpm(rdev);
1677 radeon_pm_fini_old(rdev);
1680 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1682 struct drm_device *ddev = rdev->ddev;
1686 if (rdev->pm.num_power_states < 2)
1689 mutex_lock(&rdev->pm.mutex);
1691 rdev->pm.active_crtcs = 0;
1692 rdev->pm.active_crtc_count = 0;
1693 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1698 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1699 rdev->pm.active_crtc_count++;
1704 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1705 radeon_pm_update_profile(rdev);
1706 radeon_pm_set_clocks(rdev);
1707 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1708 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1709 if (rdev->pm.active_crtc_count > 1) {
1710 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1711 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1713 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1714 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1715 radeon_pm_get_dynpm_state(rdev);
1716 radeon_pm_set_clocks(rdev);
1720 } else if (rdev->pm.active_crtc_count == 1) {
1723 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1724 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1725 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1726 radeon_pm_get_dynpm_state(rdev);
1727 radeon_pm_set_clocks(rdev);
1729 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1731 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1732 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1733 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1738 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1739 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1741 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1742 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1743 radeon_pm_get_dynpm_state(rdev);
1744 radeon_pm_set_clocks(rdev);
1750 mutex_unlock(&rdev->pm.mutex);
1753 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1755 struct drm_device *ddev = rdev->ddev;
1759 if (!rdev->pm.dpm_enabled)
1762 mutex_lock(&rdev->pm.mutex);
1765 rdev->pm.dpm.new_active_crtcs = 0;
1766 rdev->pm.dpm.new_active_crtc_count = 0;
1767 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1772 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1773 rdev->pm.dpm.new_active_crtc_count++;
1780 rdev->pm.dpm.ac_power = true;
1782 rdev->pm.dpm.ac_power = false;
1784 radeon_dpm_change_power_state_locked(rdev);
1786 mutex_unlock(&rdev->pm.mutex);
1790 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1792 if (rdev->pm.pm_method == PM_METHOD_DPM)
1793 radeon_pm_compute_clocks_dpm(rdev);
1795 radeon_pm_compute_clocks_old(rdev);
1798 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1806 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1807 if (rdev->pm.active_crtcs & (1 << crtc)) {
1808 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev,
1812 &rdev->mode_info.crtcs[crtc]->base.hwmode);
1822 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1825 bool in_vbl = radeon_pm_in_vbl(rdev);
1835 struct radeon_device *rdev;
1837 rdev = container_of(work, struct radeon_device,
1840 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1841 mutex_lock(&rdev->pm.mutex);
1842 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1847 struct radeon_ring *ring = &rdev->ring[i];
1850 not_processed += radeon_fence_count_emitted(rdev, i);
1857 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1858 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1859 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1860 rdev->pm.dynpm_can_upclock) {
1861 rdev->pm.dynpm_planned_action =
1863 rdev->pm.dynpm_action_timeout = jiffies +
1867 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1868 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1869 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1870 rdev->pm.dynpm_can_downclock) {
1871 rdev->pm.dynpm_planned_action =
1873 rdev->pm.dynpm_action_timeout = jiffies +
1881 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1882 jiffies > rdev->pm.dynpm_action_timeout) {
1883 radeon_pm_get_dynpm_state(rdev);
1884 radeon_pm_set_clocks(rdev);
1887 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1890 mutex_unlock(&rdev->pm.mutex);
1891 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1903 struct radeon_device *rdev = dev->dev_private;
1904 struct drm_device *ddev = rdev->ddev;
1906 if ((rdev->flags & RADEON_IS_PX) &&
1909 } else if (rdev->pm.dpm_enabled) {
1910 mutex_lock(&rdev->pm.mutex);
1911 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1912 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1915 mutex_unlock(&rdev->pm.mutex);
1917 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1919 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1920 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1922 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1923 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1924 if (rdev->asic->pm.get_memory_clock)
1925 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1926 if (rdev->pm.current_vddc)
1927 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1928 if (rdev->asic->pm.get_pcie_lanes)
1929 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1940 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1943 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));