Lines Matching refs:pm
68 for (i = 0; i < rdev->pm.num_power_states; i++) {
69 if (rdev->pm.power_state[i].type == ps_type) {
76 return rdev->pm.default_power_state_index;
81 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
82 mutex_lock(&rdev->pm.mutex);
84 rdev->pm.dpm.ac_power = true;
86 rdev->pm.dpm.ac_power = false;
89 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
91 mutex_unlock(&rdev->pm.mutex);
92 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
93 if (rdev->pm.profile == PM_PROFILE_AUTO) {
94 mutex_lock(&rdev->pm.mutex);
97 mutex_unlock(&rdev->pm.mutex);
104 switch (rdev->pm.profile) {
106 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
110 if (rdev->pm.active_crtc_count > 1)
111 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
113 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
115 if (rdev->pm.active_crtc_count > 1)
116 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
118 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
122 if (rdev->pm.active_crtc_count > 1)
123 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
125 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
128 if (rdev->pm.active_crtc_count > 1)
129 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
131 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
134 if (rdev->pm.active_crtc_count > 1)
135 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
137 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
141 if (rdev->pm.active_crtc_count == 0) {
142 rdev->pm.requested_power_state_index =
143 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
144 rdev->pm.requested_clock_mode_index =
145 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
147 rdev->pm.requested_power_state_index =
148 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
149 rdev->pm.requested_clock_mode_index =
150 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
169 if (rdev->pm.active_crtcs) {
174 rdev->pm.vblank_sync = false;
178 rdev->pm.vblank_sync);
181 rdev->pm.vblank_sync = false;
183 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
194 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
195 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
199 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
200 clock_info[rdev->pm.requested_clock_mode_index].sclk;
201 if (sclk > rdev->pm.default_sclk)
202 sclk = rdev->pm.default_sclk;
208 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
210 rdev->pm.active_crtc_count &&
211 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
212 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
213 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
214 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
216 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
217 clock_info[rdev->pm.requested_clock_mode_index].mclk;
219 if (mclk > rdev->pm.default_mclk)
220 mclk = rdev->pm.default_mclk;
223 if (sclk < rdev->pm.current_sclk)
228 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
240 if (sclk != rdev->pm.current_sclk) {
244 rdev->pm.current_sclk = sclk;
249 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
253 rdev->pm.current_mclk = mclk;
263 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
264 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
266 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
275 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
276 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
279 down_write(&rdev->pm.mclk_lock);
292 up_write(&rdev->pm.mclk_lock);
302 if (rdev->pm.active_crtcs & (1 << i)) {
305 rdev->pm.req_vblank |= (1 << i);
319 if (rdev->pm.req_vblank & (1 << i)) {
320 rdev->pm.req_vblank &= ~(1 << i);
329 if (rdev->pm.active_crtc_count)
332 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
335 up_write(&rdev->pm.mclk_lock);
344 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
345 for (i = 0; i < rdev->pm.num_power_states; i++) {
346 power_state = &rdev->pm.power_state[i];
349 if (i == rdev->pm.default_power_state_index)
379 int cp = rdev->pm.profile;
401 mutex_lock(&rdev->pm.mutex);
402 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
404 rdev->pm.profile = PM_PROFILE_DEFAULT;
406 rdev->pm.profile = PM_PROFILE_AUTO;
408 rdev->pm.profile = PM_PROFILE_LOW;
410 rdev->pm.profile = PM_PROFILE_MID;
412 rdev->pm.profile = PM_PROFILE_HIGH;
423 mutex_unlock(&rdev->pm.mutex);
434 int pm = rdev->pm.pm_method;
437 (pm == PM_METHOD_DYNPM) ? "dynpm" :
438 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
457 if (rdev->pm.pm_method == PM_METHOD_DPM) {
463 mutex_lock(&rdev->pm.mutex);
464 rdev->pm.pm_method = PM_METHOD_DYNPM;
465 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
466 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
467 mutex_unlock(&rdev->pm.mutex);
469 mutex_lock(&rdev->pm.mutex);
471 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
472 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
473 rdev->pm.pm_method = PM_METHOD_PROFILE;
474 mutex_unlock(&rdev->pm.mutex);
475 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
491 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
494 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
495 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
506 mutex_lock(&rdev->pm.mutex);
508 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
510 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
512 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
514 mutex_unlock(&rdev->pm.mutex);
518 mutex_unlock(&rdev->pm.mutex);
535 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
561 mutex_lock(&rdev->pm.mutex);
573 if (rdev->pm.dpm.thermal_active) {
582 mutex_unlock(&rdev->pm.mutex);
703 if (rdev->asic->pm.get_temperature)
720 temp = rdev->pm.dpm.thermal.min_temp;
722 temp = rdev->pm.dpm.thermal.max_temp;
755 if (rdev->pm.pm_method != PM_METHOD_DPM &&
765 if (rdev->pm.no_fan &&
811 switch (rdev->pm.int_thermal_type) {
820 if (rdev->asic->pm.get_temperature == NULL)
822 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
825 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
826 err = PTR_ERR(rdev->pm.int_hwmon_dev);
842 if (rdev->pm.int_hwmon_dev)
843 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
851 pm.dpm.thermal.work);
855 if (!rdev->pm.dpm_enabled)
858 if (rdev->asic->pm.get_temperature) {
861 if (temp < rdev->pm.dpm.thermal.min_temp)
863 dpm_state = rdev->pm.dpm.user_state;
865 if (rdev->pm.dpm.thermal.high_to_low)
867 dpm_state = rdev->pm.dpm.user_state;
869 mutex_lock(&rdev->pm.mutex);
871 rdev->pm.dpm.thermal_active = true;
873 rdev->pm.dpm.thermal_active = false;
874 rdev->pm.dpm.state = dpm_state;
875 mutex_unlock(&rdev->pm.mutex);
882 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
919 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
920 ps = &rdev->pm.dpm.ps[i];
953 if (rdev->pm.dpm.uvd_ps)
954 return rdev->pm.dpm.uvd_ps;
974 return rdev->pm.dpm.boot_ps;
1003 if (rdev->pm.dpm.uvd_ps) {
1004 return rdev->pm.dpm.uvd_ps;
1036 if (!rdev->pm.dpm_enabled)
1039 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
1041 if ((!rdev->pm.dpm.thermal_active) &&
1042 (!rdev->pm.dpm.uvd_active))
1043 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
1045 dpm_state = rdev->pm.dpm.state;
1049 rdev->pm.dpm.requested_ps = ps;
1054 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
1056 if (ps->vce_active != rdev->pm.dpm.vce_active)
1059 if (rdev->pm.dpm.single_display != single_display)
1065 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
1070 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1071 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1079 if (rdev->pm.dpm.new_active_crtcs ==
1080 rdev->pm.dpm.current_active_crtcs) {
1083 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
1084 (rdev->pm.dpm.new_active_crtc_count > 1)) {
1089 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1090 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1100 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
1102 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
1105 down_write(&rdev->pm.mclk_lock);
1109 ps->vce_active = rdev->pm.dpm.vce_active;
1131 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
1135 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1136 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1137 rdev->pm.dpm.single_display = single_display;
1140 if (rdev->pm.dpm.thermal_active) {
1141 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1145 rdev->pm.dpm.forced_level = level;
1148 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
1154 up_write(&rdev->pm.mclk_lock);
1162 mutex_lock(&rdev->pm.mutex);
1165 enable |= rdev->pm.dpm.sd > 0;
1166 enable |= rdev->pm.dpm.hd > 0;
1169 mutex_unlock(&rdev->pm.mutex);
1172 mutex_lock(&rdev->pm.mutex);
1173 rdev->pm.dpm.uvd_active = true;
1176 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
1178 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
1180 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
1182 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
1187 rdev->pm.dpm.state = dpm_state;
1188 mutex_unlock(&rdev->pm.mutex);
1190 mutex_lock(&rdev->pm.mutex);
1191 rdev->pm.dpm.uvd_active = false;
1192 mutex_unlock(&rdev->pm.mutex);
1202 mutex_lock(&rdev->pm.mutex);
1203 rdev->pm.dpm.vce_active = true;
1205 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1206 mutex_unlock(&rdev->pm.mutex);
1208 mutex_lock(&rdev->pm.mutex);
1209 rdev->pm.dpm.vce_active = false;
1210 mutex_unlock(&rdev->pm.mutex);
1218 mutex_lock(&rdev->pm.mutex);
1219 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1220 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1221 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1223 mutex_unlock(&rdev->pm.mutex);
1225 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1230 mutex_lock(&rdev->pm.mutex);
1234 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1235 rdev->pm.dpm_enabled = false;
1236 mutex_unlock(&rdev->pm.mutex);
1241 if (rdev->pm.pm_method == PM_METHOD_DPM)
1253 if (rdev->pm.default_vddc)
1254 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1256 if (rdev->pm.default_vddci)
1257 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1259 if (rdev->pm.default_sclk)
1260 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1261 if (rdev->pm.default_mclk)
1262 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1265 mutex_lock(&rdev->pm.mutex);
1266 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1267 rdev->pm.current_clock_mode_index = 0;
1268 rdev->pm.current_sclk = rdev->pm.default_sclk;
1269 rdev->pm.current_mclk = rdev->pm.default_mclk;
1270 if (rdev->pm.power_state) {
1271 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1272 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1274 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1275 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1276 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1277 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1280 mutex_unlock(&rdev->pm.mutex);
1289 mutex_lock(&rdev->pm.mutex);
1290 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1293 mutex_unlock(&rdev->pm.mutex);
1296 rdev->pm.dpm_enabled = true;
1304 if (rdev->pm.default_vddc)
1305 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1307 if (rdev->pm.default_vddci)
1308 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1310 if (rdev->pm.default_sclk)
1311 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1312 if (rdev->pm.default_mclk)
1313 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1319 if (rdev->pm.pm_method == PM_METHOD_DPM)
1329 rdev->pm.profile = PM_PROFILE_DEFAULT;
1330 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1331 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1332 rdev->pm.dynpm_can_upclock = true;
1333 rdev->pm.dynpm_can_downclock = true;
1334 rdev->pm.default_sclk = rdev->clock.default_sclk;
1335 rdev->pm.default_mclk = rdev->clock.default_mclk;
1336 rdev->pm.current_sclk = rdev->clock.default_sclk;
1337 rdev->pm.current_mclk = rdev->clock.default_mclk;
1338 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1351 if (rdev->pm.default_vddc)
1352 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1354 if (rdev->pm.default_vddci)
1355 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1357 if (rdev->pm.default_sclk)
1358 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1359 if (rdev->pm.default_mclk)
1360 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1369 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1372 if (rdev->pm.num_power_states > 1) {
1374 DRM_ERROR("Failed to register debugfs file for PM!\n");
1388 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1390 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1399 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1400 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1401 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1402 rdev->pm.default_sclk = rdev->clock.default_sclk;
1403 rdev->pm.default_mclk = rdev->clock.default_mclk;
1404 rdev->pm.current_sclk = rdev->clock.default_sclk;
1405 rdev->pm.current_mclk = rdev->clock.default_mclk;
1406 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1418 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1419 mutex_lock(&rdev->pm.mutex);
1421 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1426 mutex_unlock(&rdev->pm.mutex);
1429 rdev->pm.dpm_enabled = true;
1440 rdev->pm.dpm_enabled = false;
1444 if (rdev->pm.default_vddc)
1445 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1447 if (rdev->pm.default_vddci)
1448 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1450 if (rdev->pm.default_sclk)
1451 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1452 if (rdev->pm.default_mclk)
1453 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1504 rdev->pm.pm_method = PM_METHOD_PROFILE;
1508 rdev->pm.pm_method = PM_METHOD_PROFILE;
1510 rdev->pm.pm_method = PM_METHOD_DPM;
1512 rdev->pm.pm_method = PM_METHOD_PROFILE;
1542 rdev->pm.pm_method = PM_METHOD_PROFILE;
1546 rdev->pm.pm_method = PM_METHOD_PROFILE;
1548 rdev->pm.pm_method = PM_METHOD_PROFILE;
1550 rdev->pm.pm_method = PM_METHOD_PROFILE;
1552 rdev->pm.pm_method = PM_METHOD_DPM;
1556 rdev->pm.pm_method = PM_METHOD_PROFILE;
1560 if (rdev->pm.pm_method == PM_METHOD_DPM)
1570 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1571 if (rdev->pm.dpm_enabled) {
1573 if (!rdev->pm.sysfs_initialized) {
1587 rdev->pm.sysfs_initialized = true;
1591 mutex_lock(&rdev->pm.mutex);
1593 mutex_unlock(&rdev->pm.mutex);
1595 rdev->pm.dpm_enabled = false;
1605 if ((rdev->pm.num_power_states > 1) &&
1606 (!rdev->pm.sysfs_initialized)) {
1616 rdev->pm.sysfs_initialized = true;
1625 if (rdev->pm.num_power_states > 1) {
1626 mutex_lock(&rdev->pm.mutex);
1627 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1628 rdev->pm.profile = PM_PROFILE_DEFAULT;
1631 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1633 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1634 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1637 mutex_unlock(&rdev->pm.mutex);
1639 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1648 kfree(rdev->pm.power_state);
1653 if (rdev->pm.num_power_states > 1) {
1654 mutex_lock(&rdev->pm.mutex);
1656 mutex_unlock(&rdev->pm.mutex);
1669 kfree(rdev->pm.power_state);
1674 if (rdev->pm.pm_method == PM_METHOD_DPM)
1686 if (rdev->pm.num_power_states < 2)
1689 mutex_lock(&rdev->pm.mutex);
1691 rdev->pm.active_crtcs = 0;
1692 rdev->pm.active_crtc_count = 0;
1698 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1699 rdev->pm.active_crtc_count++;
1704 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1707 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1708 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1709 if (rdev->pm.active_crtc_count > 1) {
1710 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1711 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1713 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1714 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1720 } else if (rdev->pm.active_crtc_count == 1) {
1723 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1724 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1725 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1729 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1731 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1732 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1733 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1738 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1739 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1741 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1742 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1750 mutex_unlock(&rdev->pm.mutex);
1759 if (!rdev->pm.dpm_enabled)
1762 mutex_lock(&rdev->pm.mutex);
1765 rdev->pm.dpm.new_active_crtcs = 0;
1766 rdev->pm.dpm.new_active_crtc_count = 0;
1772 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1773 rdev->pm.dpm.new_active_crtc_count++;
1780 rdev->pm.dpm.ac_power = true;
1782 rdev->pm.dpm.ac_power = false;
1786 mutex_unlock(&rdev->pm.mutex);
1792 if (rdev->pm.pm_method == PM_METHOD_DPM)
1807 if (rdev->pm.active_crtcs & (1 << crtc)) {
1828 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1838 pm.dynpm_idle_work.work);
1841 mutex_lock(&rdev->pm.mutex);
1842 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1857 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1858 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1859 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1860 rdev->pm.dynpm_can_upclock) {
1861 rdev->pm.dynpm_planned_action =
1863 rdev->pm.dynpm_action_timeout = jiffies +
1867 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1868 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1869 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1870 rdev->pm.dynpm_can_downclock) {
1871 rdev->pm.dynpm_planned_action =
1873 rdev->pm.dynpm_action_timeout = jiffies +
1881 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1882 jiffies > rdev->pm.dynpm_action_timeout) {
1887 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1890 mutex_unlock(&rdev->pm.mutex);
1909 } else if (rdev->pm.dpm_enabled) {
1910 mutex_lock(&rdev->pm.mutex);
1915 mutex_unlock(&rdev->pm.mutex);
1917 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1920 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1923 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1924 if (rdev->asic->pm.get_memory_clock)
1926 if (rdev->pm.current_vddc)
1927 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1928 if (rdev->asic->pm.get_pcie_lanes)
Indexes created Sat Sep 20 22:09:52 GMT 2025