Lines Matching refs:gart
636 * PCI GART
642 * entry otherwise if first GPU GART read hit this entry it
650 if (rdev->gart.ptr) {
651 WARN(1, "R100 PCI GART already initialized\n");
654 /* Initialize common gart structure */
658 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
659 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
660 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
661 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
675 /* set PCI GART page-table base address */
676 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
680 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
682 (unsigned long long)rdev->gart.table_addr);
683 rdev->gart.ready = true;
706 u32 *gtt = rdev->gart.ptr;
3922 /* Initialize GART (initialize after TTM so we can allocate
3971 /* Make sur GART are not working */
Indexes created Sat Oct 18 08:10:09 GMT 2025