Lines Matching refs:rdev
82 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
97 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
117 * @rdev: radeon_device pointer
122 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
126 if (crtc >= rdev->num_crtc)
140 while (r100_is_in_vblank(rdev, crtc)) {
142 if (!r100_is_counter_moving(rdev, crtc))
147 while (!r100_is_in_vblank(rdev, crtc)) {
149 if (!r100_is_counter_moving(rdev, crtc))
158 * @rdev: radeon_device pointer
167 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
169 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
178 for (i = 0; i < rdev->usec_timeout; i++) {
194 * @rdev: radeon_device pointer
200 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
202 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
212 * @rdev: radeon_device pointer
218 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
221 rdev->pm.dynpm_can_upclock = true;
222 rdev->pm.dynpm_can_downclock = true;
224 switch (rdev->pm.dynpm_planned_action) {
226 rdev->pm.requested_power_state_index = 0;
227 rdev->pm.dynpm_can_downclock = false;
230 if (rdev->pm.current_power_state_index == 0) {
231 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
232 rdev->pm.dynpm_can_downclock = false;
234 if (rdev->pm.active_crtc_count > 1) {
235 for (i = 0; i < rdev->pm.num_power_states; i++) {
236 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
238 else if (i >= rdev->pm.current_power_state_index) {
239 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
242 rdev->pm.requested_power_state_index = i;
247 rdev->pm.requested_power_state_index =
248 rdev->pm.current_power_state_index - 1;
251 if ((rdev->pm.active_crtc_count > 0) &&
252 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
254 rdev->pm.requested_power_state_index++;
258 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
259 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
260 rdev->pm.dynpm_can_upclock = false;
262 if (rdev->pm.active_crtc_count > 1) {
263 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
264 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
266 else if (i <= rdev->pm.current_power_state_index) {
267 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
270 rdev->pm.requested_power_state_index = i;
275 rdev->pm.requested_power_state_index =
276 rdev->pm.current_power_state_index + 1;
280 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
281 rdev->pm.dynpm_can_upclock = false;
289 rdev->pm.requested_clock_mode_index = 0;
292 rdev->pm.power_state[rdev->pm.requested_power_state_index].
293 clock_info[rdev->pm.requested_clock_mode_index].sclk,
294 rdev->pm.power_state[rdev->pm.requested_power_state_index].
295 clock_info[rdev->pm.requested_clock_mode_index].mclk,
296 rdev->pm.power_state[rdev->pm.requested_power_state_index].
303 * @rdev: radeon_device pointer
309 void r100_pm_init_profile(struct radeon_device *rdev)
312 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
313 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
314 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
329 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
334 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
337 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
339 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
344 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
351 * @rdev: radeon_device pointer
356 void r100_pm_misc(struct radeon_device *rdev)
358 int requested_index = rdev->pm.requested_power_state_index;
359 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
436 if ((rdev->flags & RADEON_IS_PCIE) &&
437 !(rdev->flags & RADEON_IS_IGP) &&
438 rdev->asic->pm.set_pcie_lanes &&
440 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
441 radeon_set_pcie_lanes(rdev,
450 * @rdev: radeon_device pointer
454 void r100_pm_prepare(struct radeon_device *rdev)
456 struct drm_device *ddev = rdev->ddev;
481 * @rdev: radeon_device pointer
485 void r100_pm_finish(struct radeon_device *rdev)
487 struct drm_device *ddev = rdev->ddev;
512 * @rdev: radeon_device pointer
517 bool r100_gui_idle(struct radeon_device *rdev)
529 * @rdev: radeon_device pointer
535 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
557 * @rdev: radeon_device pointer
562 void r100_hpd_set_polarity(struct radeon_device *rdev,
566 bool connected = r100_hpd_sense(rdev, hpd);
593 * @rdev: radeon_device pointer
598 void r100_hpd_init(struct radeon_device *rdev)
600 struct drm_device *dev = rdev->ddev;
608 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
610 radeon_irq_kms_enable_hpd(rdev, enable);
616 * @rdev: radeon_device pointer
621 void r100_hpd_fini(struct radeon_device *rdev)
623 struct drm_device *dev = rdev->ddev;
632 radeon_irq_kms_disable_hpd(rdev, disable);
638 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
646 int r100_pci_gart_init(struct radeon_device *rdev)
650 if (rdev->gart.ptr) {
655 r = radeon_gart_init(rdev);
658 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
659 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
660 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
661 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
662 return radeon_gart_table_ram_alloc(rdev);
665 int r100_pci_gart_enable(struct radeon_device *rdev)
673 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
674 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
676 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
679 r100_pci_gart_tlb_flush(rdev);
681 (unsigned)(rdev->mc.gtt_size >> 20),
682 (unsigned long long)rdev->gart.table_addr);
683 rdev->gart.ready = true;
687 void r100_pci_gart_disable(struct radeon_device *rdev)
703 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
706 u32 *gtt = rdev->gart.ptr;
710 void r100_pci_gart_fini(struct radeon_device *rdev)
712 radeon_gart_fini(rdev);
713 r100_pci_gart_disable(rdev);
714 radeon_gart_table_ram_free(rdev);
717 int r100_irq_set(struct radeon_device *rdev)
721 if (!rdev->irq.installed) {
726 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
729 if (rdev->irq.crtc_vblank_int[0] ||
730 atomic_read(&rdev->irq.pflip[0])) {
733 if (rdev->irq.crtc_vblank_int[1] ||
734 atomic_read(&rdev->irq.pflip[1])) {
737 if (rdev->irq.hpd[0]) {
740 if (rdev->irq.hpd[1]) {
751 void r100_irq_disable(struct radeon_device *rdev)
762 static uint32_t r100_irq_ack(struct radeon_device *rdev)
775 int r100_irq_process(struct radeon_device *rdev)
780 status = r100_irq_ack(rdev);
784 if (rdev->shutdown) {
790 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
794 if (rdev->irq.crtc_vblank_int[0]) {
795 drm_handle_vblank(rdev->ddev, 0);
797 spin_lock(&rdev->irq.vblank_lock);
798 rdev->pm.vblank_sync = true;
799 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock);
800 spin_unlock(&rdev->irq.vblank_lock);
802 rdev->pm.vblank_sync = true;
803 wake_up(&rdev->irq.vblank_queue);
806 if (atomic_read(&rdev->irq.pflip[0]))
807 radeon_crtc_handle_vblank(rdev, 0);
810 if (rdev->irq.crtc_vblank_int[1]) {
811 drm_handle_vblank(rdev->ddev, 1);
813 spin_lock(&rdev->irq.vblank_lock);
814 rdev->pm.vblank_sync = true;
815 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock);
816 spin_unlock(&rdev->irq.vblank_lock);
818 rdev->pm.vblank_sync = true;
819 wake_up(&rdev->irq.vblank_queue);
822 if (atomic_read(&rdev->irq.pflip[1]))
823 radeon_crtc_handle_vblank(rdev, 1);
833 status = r100_irq_ack(rdev);
836 schedule_delayed_work(&rdev->hotplug_work, 0);
837 if (rdev->msi_enabled) {
838 switch (rdev->family) {
853 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
863 * rdev: radeon device structure
866 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
869 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
872 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
877 void r100_fence_ring_emit(struct radeon_device *rdev,
880 struct radeon_ring *ring = &rdev->ring[fence->ring];
891 r100_ring_hdp_flush(rdev, ring);
893 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
899 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
909 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
915 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
934 r = radeon_ring_lock(rdev, ring, ndw);
977 r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
979 radeon_ring_unlock_undo(rdev, ring);
982 radeon_ring_unlock_commit(rdev, ring, false);
986 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
991 for (i = 0; i < rdev->usec_timeout; i++) {
1001 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
1005 r = radeon_ring_lock(rdev, ring, 2);
1015 radeon_ring_unlock_commit(rdev, ring, false);
1020 static int r100_cp_init_microcode(struct radeon_device *rdev)
1027 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
1028 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
1029 (rdev->family == CHIP_RS200)) {
1032 } else if ((rdev->family == CHIP_R200) ||
1033 (rdev->family == CHIP_RV250) ||
1034 (rdev->family == CHIP_RV280) ||
1035 (rdev->family == CHIP_RS300)) {
1038 } else if ((rdev->family == CHIP_R300) ||
1039 (rdev->family == CHIP_R350) ||
1040 (rdev->family == CHIP_RV350) ||
1041 (rdev->family == CHIP_RV380) ||
1042 (rdev->family == CHIP_RS400) ||
1043 (rdev->family == CHIP_RS480)) {
1046 } else if ((rdev->family == CHIP_R420) ||
1047 (rdev->family == CHIP_R423) ||
1048 (rdev->family == CHIP_RV410)) {
1051 } else if ((rdev->family == CHIP_RS690) ||
1052 (rdev->family == CHIP_RS740)) {
1055 } else if (rdev->family == CHIP_RS600) {
1058 } else if ((rdev->family == CHIP_RV515) ||
1059 (rdev->family == CHIP_R520) ||
1060 (rdev->family == CHIP_RV530) ||
1061 (rdev->family == CHIP_R580) ||
1062 (rdev->family == CHIP_RV560) ||
1063 (rdev->family == CHIP_RV570)) {
1068 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1071 } else if (rdev->me_fw->size % 8) {
1073 rdev->me_fw->size, fw_name);
1075 release_firmware(rdev->me_fw);
1076 rdev->me_fw = NULL;
1081 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1086 if (rdev->wb.enabled)
1087 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1094 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1100 void r100_gfx_set_wptr(struct radeon_device *rdev,
1107 static void r100_cp_load_microcode(struct radeon_device *rdev)
1112 if (r100_gui_wait_for_idle(rdev)) {
1116 if (rdev->me_fw) {
1117 size = rdev->me_fw->size / 4;
1118 fw_data = (const __be32 *)rdev->me_fw->data;
1129 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1131 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1142 if (r100_debugfs_cp_init(rdev)) {
1145 if (!rdev->me_fw) {
1146 r = r100_cp_init_microcode(rdev);
1156 r100_cp_load_microcode(rdev);
1157 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1207 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1208 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1210 if (rdev->wb.enabled)
1228 pci_set_master(rdev->pdev);
1230 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1231 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1237 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1240 && radeon_ring_supports_scratch_reg(rdev, ring)) {
1241 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1250 void r100_cp_fini(struct radeon_device *rdev)
1252 if (r100_cp_wait_for_idle(rdev)) {
1256 r100_cp_disable(rdev);
1257 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1258 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1262 void r100_cp_disable(struct radeon_device *rdev)
1265 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1266 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1270 if (r100_gui_wait_for_idle(rdev)) {
1484 crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id);
1979 r = r100_cs_track_check(p->rdev, track);
1991 r = r100_cs_track_check(p->rdev, track);
2003 r = r100_cs_track_check(p->rdev, track);
2010 r = r100_cs_track_check(p->rdev, track);
2017 r = r100_cs_track_check(p->rdev, track);
2024 r = r100_cs_track_check(p->rdev, track);
2031 r = r100_cs_track_check(p->rdev, track);
2038 if (p->rdev->hyperz_filp != p->filp)
2059 r100_cs_track_clear(p->rdev, track);
2069 if (p->rdev->family >= CHIP_R200)
2071 p->rdev->config.r100.reg_safe_bm,
2072 p->rdev->config.r100.reg_safe_bm_size,
2076 p->rdev->config.r100.reg_safe_bm,
2077 p->rdev->config.r100.reg_safe_bm_size,
2143 static int r100_cs_track_cube(struct radeon_device *rdev,
2174 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2195 if (rdev->family < CHIP_R300)
2201 if (rdev->family >= CHIP_RV515)
2208 if (rdev->family >= CHIP_RV515)
2235 ret = r100_cs_track_cube(rdev, track, u);
2256 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2342 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2361 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2388 return r100_cs_track_texture_check(rdev, track);
2393 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2402 if (rdev->family < CHIP_R300) {
2404 if (rdev->family <= CHIP_RS200)
2446 if (rdev->family <= CHIP_RS200) {
2473 static void r100_errata(struct radeon_device *rdev)
2475 rdev->pll_errata = 0;
2477 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2478 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2481 if (rdev->family == CHIP_RV100 ||
2482 rdev->family == CHIP_RS100 ||
2483 rdev->family == CHIP_RS200) {
2484 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2488 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2493 for (i = 0; i < rdev->usec_timeout; i++) {
2503 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2508 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2511 for (i = 0; i < rdev->usec_timeout; i++) {
2521 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2526 for (i = 0; i < rdev->usec_timeout; i++) {
2537 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2543 radeon_ring_lockup_update(rdev, ring);
2546 return radeon_ring_test_lockup(rdev, ring);
2550 void r100_enable_bm(struct radeon_device *rdev)
2558 void r100_bm_disable(struct radeon_device *rdev)
2571 pci_clear_master(rdev->pdev);
2575 int r100_asic_reset(struct radeon_device *rdev, bool hard)
2585 r100_mc_stop(rdev, &save);
2587 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2596 pci_save_state(rdev->pdev);
2598 r100_bm_disable(rdev);
2608 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2616 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2618 pci_restore_state(rdev->pdev);
2619 r100_enable_bm(rdev);
2623 dev_err(rdev->dev, "failed to reset GPU\n");
2626 dev_info(rdev->dev, "GPU reset succeed\n");
2627 r100_mc_resume(rdev, &save);
2631 void r100_set_common_regs(struct radeon_device *rdev)
2633 struct drm_device *dev = rdev->ddev;
2718 static void r100_vram_get_type(struct radeon_device *rdev)
2722 rdev->mc.vram_is_ddr = false;
2723 if (rdev->flags & RADEON_IS_IGP)
2724 rdev->mc.vram_is_ddr = true;
2726 rdev->mc.vram_is_ddr = true;
2727 if ((rdev->family == CHIP_RV100) ||
2728 (rdev->family == CHIP_RS100) ||
2729 (rdev->family == CHIP_RS200)) {
2732 rdev->mc.vram_width = 32;
2734 rdev->mc.vram_width = 64;
2736 if (rdev->flags & RADEON_SINGLE_CRTC) {
2737 rdev->mc.vram_width /= 4;
2738 rdev->mc.vram_is_ddr = true;
2740 } else if (rdev->family <= CHIP_RV280) {
2743 rdev->mc.vram_width = 128;
2745 rdev->mc.vram_width = 64;
2749 rdev->mc.vram_width = 128;
2753 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2763 if (rdev->family == CHIP_RV280 ||
2764 rdev->family >= CHIP_RV350) {
2775 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2791 void r100_vram_init_sizes(struct radeon_device *rdev)
2796 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2797 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2798 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2800 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2801 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2803 if (rdev->flags & RADEON_IS_IGP) {
2807 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2808 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2809 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2811 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2815 if (rdev->mc.real_vram_size == 0) {
2816 rdev->mc.real_vram_size = 8192 * 1024;
2817 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2822 if (rdev->mc.aper_size > config_aper_size)
2823 config_aper_size = rdev->mc.aper_size;
2825 if (config_aper_size > rdev->mc.real_vram_size)
2826 rdev->mc.mc_vram_size = config_aper_size;
2828 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2832 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2846 static void r100_mc_init(struct radeon_device *rdev)
2850 r100_vram_get_type(rdev);
2851 r100_vram_init_sizes(rdev);
2852 base = rdev->mc.aper_base;
2853 if (rdev->flags & RADEON_IS_IGP)
2855 radeon_vram_location(rdev, &rdev->mc, base);
2856 rdev->mc.gtt_base_align = 0;
2857 if (!(rdev->flags & RADEON_IS_AGP))
2858 radeon_gtt_location(rdev, &rdev->mc);
2859 radeon_update_bandwidth_info(rdev);
2866 void r100_pll_errata_after_index(struct radeon_device *rdev)
2868 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2874 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2879 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2888 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2899 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2904 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2906 r100_pll_errata_after_index(rdev);
2908 r100_pll_errata_after_data(rdev);
2909 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2913 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2917 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2919 r100_pll_errata_after_index(rdev);
2921 r100_pll_errata_after_data(rdev);
2922 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2925 static void r100_set_safe_registers(struct radeon_device *rdev)
2927 if (ASIC_IS_RN50(rdev)) {
2928 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2929 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2930 } else if (rdev->family < CHIP_R200) {
2931 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2932 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2934 r200_set_safe_registers(rdev);
2946 struct radeon_device *rdev = dev->dev_private;
2967 struct radeon_device *rdev = dev->dev_private;
2968 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2972 radeon_ring_free_size(rdev, ring);
2995 struct radeon_device *rdev = dev->dev_private;
3045 struct radeon_device *rdev = dev->dev_private;
3085 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3088 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3094 int r100_debugfs_cp_init(struct radeon_device *rdev)
3097 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3103 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3106 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3112 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3119 if (rdev->family <= CHIP_RS200) {
3129 } else if (rdev->family <= CHIP_RV280) {
3147 if (rdev->family < CHIP_R300)
3160 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3166 void r100_bandwidth_update(struct radeon_device *rdev)
3241 if (!rdev->mode_info.mode_config_initialized)
3247 radeon_update_display_priority(rdev);
3249 if (rdev->mode_info.crtcs[0]->base.enabled) {
3251 rdev->mode_info.crtcs[0]->base.primary->fb;
3253 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3256 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3257 if (rdev->mode_info.crtcs[1]->base.enabled) {
3259 rdev->mode_info.crtcs[1]->base.primary->fb;
3261 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3268 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3283 sclk_ff = rdev->pm.sclk;
3284 mclk_ff = rdev->pm.mclk;
3286 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3316 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3320 } else if (rdev->family == CHIP_R300 ||
3321 rdev->family == CHIP_R350) { /* r300, r350 */
3325 } else if (rdev->family == CHIP_RV350 ||
3326 rdev->family == CHIP_RV380) {
3331 } else if (rdev->family == CHIP_R420 ||
3332 rdev->family == CHIP_R423 ||
3333 rdev->family == CHIP_RV410) {
3357 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3358 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3365 if (rdev->family == CHIP_RS400 ||
3366 rdev->family == CHIP_RS480) {
3373 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3394 if (rdev->family == CHIP_RV410 ||
3395 rdev->family == CHIP_R420 ||
3396 rdev->family == CHIP_R423)
3405 if (rdev->flags & RADEON_IS_AGP) {
3413 if (ASIC_IS_R300(rdev)) {
3416 if ((rdev->family == CHIP_RV100) ||
3417 rdev->flags & RADEON_IS_IGP) {
3418 if (rdev->mc.vram_is_ddr)
3423 if (rdev->mc.vram_width == 128)
3432 if (rdev->mc.vram_is_ddr) {
3433 if (rdev->mc.vram_width == 32) {
3460 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3482 if (ASIC_IS_RV100(rdev))
3511 if (rdev->disp_priority == 2) {
3522 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3531 if ((rdev->family == CHIP_R350) &&
3547 if ((rdev->family == CHIP_RS400) ||
3548 (rdev->family == CHIP_RS480)) {
3587 if ((rdev->family == CHIP_R350) &&
3597 if ((rdev->family == CHIP_RS100) ||
3598 (rdev->family == CHIP_RS200))
3601 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3621 if (rdev->disp_priority == 2) {
3630 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3638 if ((rdev->family == CHIP_RS400) ||
3639 (rdev->family == CHIP_RS480)) {
3667 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
3670 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
3673 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3680 r = radeon_scratch_get(rdev, &scratch);
3686 r = radeon_ring_lock(rdev, ring, 2);
3689 radeon_scratch_free(rdev, scratch);
3694 radeon_ring_unlock_commit(rdev, ring, false);
3695 for (i = 0; i < rdev->usec_timeout; i++) {
3702 if (i < rdev->usec_timeout) {
3709 radeon_scratch_free(rdev, scratch);
3713 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3715 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3728 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3736 r = radeon_scratch_get(rdev, &scratch);
3742 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3756 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3772 for (i = 0; i < rdev->usec_timeout; i++) {
3779 if (i < rdev->usec_timeout) {
3787 radeon_ib_free(rdev, &ib);
3789 radeon_scratch_free(rdev, scratch);
3793 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3798 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3806 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3823 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3835 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3838 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3839 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3840 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3846 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3851 void r100_vga_render_disable(struct radeon_device *rdev)
3859 static void r100_debugfs(struct radeon_device *rdev)
3863 r = r100_debugfs_mc_info_init(rdev);
3865 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3868 static void r100_mc_program(struct radeon_device *rdev)
3873 r100_mc_stop(rdev, &save);
3874 if (rdev->flags & RADEON_IS_AGP) {
3876 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3877 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3878 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3879 if (rdev->family > CHIP_RV200)
3881 upper_32_bits(rdev->mc.agp_base) & 0xff);
3885 if (rdev->family > CHIP_RV200)
3889 if (r100_mc_wait_for_idle(rdev))
3890 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3893 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3894 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3895 r100_mc_resume(rdev, &save);
3898 static void r100_clock_startup(struct radeon_device *rdev)
3903 radeon_legacy_set_clock_gating(rdev, 1);
3907 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3912 static int r100_startup(struct radeon_device *rdev)
3917 r100_set_common_regs(rdev);
3919 r100_mc_program(rdev);
3921 r100_clock_startup(rdev);
3924 r100_enable_bm(rdev);
3925 if (rdev->flags & RADEON_IS_PCI) {
3926 r = r100_pci_gart_enable(rdev);
3932 r = radeon_wb_init(rdev);
3936 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3938 dev_err(rdev
3943 if (!rdev->irq.installed) {
3944 r = radeon_irq_kms_init(rdev);
3949 r100_irq_set(rdev);
3950 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3952 r = r100_cp_init(rdev, 1024 * 1024);
3954 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3958 r = radeon_ib_pool_init(rdev);
3960 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3967 int r100_resume(struct radeon_device *rdev)
3972 if (rdev->flags & RADEON_IS_PCI)
3973 r100_pci_gart_disable(rdev);
3975 r100_clock_startup(rdev);
3977 if (radeon_asic_reset(rdev)) {
3978 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3983 radeon_combios_asic_init(rdev->ddev);
3985 r100_clock_startup(rdev);
3987 radeon_surface_init(rdev);
3989 rdev->accel_working = true;
3990 r = r100_startup(rdev);
3992 rdev->accel_working = false;
3997 int r100_suspend(struct radeon_device *rdev)
3999 radeon_pm_suspend(rdev);
4000 r100_cp_disable(rdev);
4001 radeon_wb_disable(rdev);
4002 r100_irq_disable(rdev);
4003 if (rdev->flags & RADEON_IS_PCI)
4004 r100_pci_gart_disable(rdev);
4008 void r100_fini(struct radeon_device *rdev)
4010 radeon_pm_fini(rdev);
4011 r100_cp_fini(rdev);
4012 radeon_wb_fini(rdev);
4013 radeon_ib_pool_fini(rdev);
4014 radeon_gem_fini(rdev);
4015 if (rdev->flags & RADEON_IS_PCI)
4016 r100_pci_gart_fini(rdev);
4017 radeon_agp_fini(rdev);
4018 radeon_irq_kms_fini(rdev);
4019 radeon_fence_driver_fini(rdev);
4020 radeon_bo_fini(rdev);
4021 radeon_atombios_fini(rdev);
4022 kfree(rdev->bios);
4023 rdev->bios = NULL;
4033 void r100_restore_sanity(struct radeon_device *rdev)
4051 int r100_init(struct radeon_device *rdev)
4056 r100_debugfs(rdev);
4058 r100_vga_render_disable(rdev);
4060 radeon_scratch_init(rdev);
4062 radeon_surface_init(rdev);
4064 r100_restore_sanity(rdev);
4067 if (!radeon_get_bios(rdev)) {
4068 if (ASIC_IS_AVIVO(rdev))
4071 if (rdev->is_atom_bios) {
4072 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4075 r = radeon_combios_init(rdev);
4080 if (radeon_asic_reset(rdev)) {
4081 dev_warn(rdev->dev,
4087 if (radeon_boot_test_post_card(rdev) == false)
4090 r100_errata(rdev);
4092 radeon_get_clock_info(rdev->ddev);
4094 if (rdev->flags & RADEON_IS_AGP) {
4095 r = radeon_agp_init(rdev);
4097 radeon_agp_disable(rdev);
4101 r100_mc_init(rdev);
4103 r = radeon_fence_driver_init(rdev);
4107 r = radeon_bo_init(rdev);
4110 if (rdev->flags & RADEON_IS_PCI) {
4111 r = r100_pci_gart_init(rdev);
4115 r100_set_safe_registers(rdev);
4118 radeon_pm_init(rdev);
4120 rdev->accel_working = true;
4121 r = r100_startup(rdev);
4124 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4125 r100_cp_fini(rdev);
4126 radeon_wb_fini(rdev);
4127 radeon_ib_pool_fini(rdev);
4128 radeon_irq_kms_fini(rdev);
4129 if (rdev->flags & RADEON_IS_PCI)
4130 r100_pci_gart_fini(rdev);
4131 rdev->accel_working = false;
4136 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
4141 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4143 bus_space_write_4(rdev->rmmio_bst, rdev->rmmio_bsh,
4145 ret = bus_space_read_4(rdev->rmmio_bst, rdev->rmmio_bsh,
4148 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4149 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4151 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4155 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4159 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4161 bus_space_write_4(rdev->rmmio_bst, rdev->rmmio_bsh,
4163 bus_space_write_4(rdev->rmmio_bst, rdev->rmmio_bsh,
4166 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4167 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4169 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4172 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4175 if (reg < rdev->rio_mem_size) {
4176 return bus_space_read_4(rdev->rio_mem_bst, rdev->rio_mem_bsh,
4179 bus_space_write_4(rdev->rio_mem_bst, rdev->rio_mem_bsh,
4181 return bus_space_read_4(rdev->rio_mem_bst, rdev->rio_mem_bsh,
4185 if (reg < rdev->rio_mem_size)
4186 return ioread32(rdev->rio_mem + reg);
4188 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4189 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4194 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4197 if (reg < rdev->rio_mem_size) {
4198 bus_space_write_4(rdev->rio_mem_bst, rdev->rio_mem_bsh, reg,
4201 bus_space_write_4(rdev->rio_mem_bst, rdev->rio_mem_bsh,
4203 bus_space_write_4(rdev->rio_mem_bst, rdev->rio_mem_bsh,
4207 if (reg < rdev->rio_mem_size)
4208 iowrite32(v, rdev->rio_mem + reg);
4210 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4211 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
Indexes created Wed Oct 15 02:09:48 GMT 2025