Lines Matching refs:rdev
66 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
71 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
72 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
74 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
78 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
82 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
83 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
85 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
91 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
93 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
144 void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
147 void __iomem *ptr = rdev->gart.ptr;
160 int rv370_pcie_gart_init(struct radeon_device *rdev)
164 if (rdev->gart.robj) {
169 r = radeon_gart_init(rdev);
172 r = rv370_debugfs_pcie_gart_info_init(rdev);
175 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
176 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
177 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
178 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
179 return radeon_gart_table_vram_alloc(rdev);
182 int rv370_pcie_gart_enable(struct radeon_device *rdev)
188 if (rdev->gart.robj == NULL) {
189 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
192 r = radeon_gart_table_vram_pin(rdev);
198 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
199 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
203 table_addr = rdev->gart.table_addr;
206 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
214 rv370_pcie_gart_tlb_flush(rdev);
216 (unsigned)(rdev->mc.gtt_size >> 20),
218 rdev->gart.ready = true;
222 void rv370_pcie_gart_disable(struct radeon_device *rdev)
233 radeon_gart_table_vram_unpin(rdev);
236 void rv370_pcie_gart_fini(struct radeon_device *rdev)
238 radeon_gart_fini(rdev);
239 rv370_pcie_gart_disable(rdev);
240 radeon_gart_table_vram_free(rdev);
243 void r300_fence_ring_emit(struct radeon_device *rdev,
246 struct radeon_ring *ring = &rdev->ring[fence->ring];
266 radeon_ring_write(ring, rdev->config.r300.hdp_cntl |
269 radeon_ring_write(ring, rdev->config.r300.hdp_cntl);
271 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
277 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
284 switch(rdev->num_gb_pipes) {
300 r = radeon_ring_lock(rdev, ring, 64);
364 radeon_ring_unlock_commit(rdev, ring, false);
367 static void r300_errata(struct radeon_device *rdev)
369 rdev->pll_errata = 0;
371 if (rdev->family == CHIP_R300 &&
373 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
377 int r300_mc_wait_for_idle(struct radeon_device *rdev)
382 for (i = 0; i < rdev->usec_timeout; i++) {
393 static void r300_gpu_init(struct radeon_device *rdev)
397 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
398 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
400 rdev->num_gb_pipes = 2;
403 rdev->num_gb_pipes = 1;
405 rdev->num_z_pipes = 1;
407 switch (rdev->num_gb_pipes) {
424 if (r100_gui_wait_for_idle(rdev)) {
435 if (r100_gui_wait_for_idle(rdev)) {
438 if (r300_mc_wait_for_idle(rdev)) {
442 rdev->num_gb_pipes, rdev->num_z_pipes);
445 int r300_asic_reset(struct radeon_device *rdev, bool hard)
455 r100_mc_stop(rdev, &save);
457 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
466 pci_save_state(rdev->pdev);
468 r100_bm_disable(rdev);
476 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
488 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
490 pci_restore_state(rdev->pdev);
491 r100_enable_bm(rdev);
494 dev_err(rdev->dev, "failed to reset GPU\n");
497 dev_info(rdev->dev, "GPU reset succeed\n");
498 r100_mc_resume(rdev, &save);
505 void r300_mc_init(struct radeon_device *rdev)
511 rdev->mc.vram_is_ddr = true;
515 case 0: rdev->mc.vram_width = 64; break;
516 case 1: rdev->mc.vram_width = 128; break;
517 case 2: rdev->mc.vram_width = 256; break;
518 default: rdev->mc.vram_width = 128; break;
520 r100_vram_init_sizes(rdev);
521 base = rdev->mc.aper_base;
522 if (rdev->flags & RADEON_IS_IGP)
524 radeon_vram_location(rdev, &rdev->mc, base);
525 rdev->mc.gtt_base_align = 0;
526 if (!(rdev->flags & RADEON_IS_AGP))
527 radeon_gtt_location(rdev, &rdev->mc);
528 radeon_update_bandwidth_info(rdev);
531 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
535 if (rdev->flags & RADEON_IS_IGP)
538 if (!(rdev->flags & RADEON_IS_PCIE))
590 int rv370_get_pcie_lanes(struct radeon_device *rdev)
594 if (rdev->flags & RADEON_IS_IGP)
597 if (!(rdev->flags & RADEON_IS_PCIE))
626 struct radeon_device *rdev = dev->dev_private;
651 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
654 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
781 if (p->rdev->family < CHIP_RV515)
788 if (p->rdev->family < CHIP_RV515) {
797 p->rdev->cmask_filp != p->filp) {
847 if (p->rdev->family < CHIP_RV515) {
997 if (p->rdev->family < CHIP_R420) {
1064 if (p->rdev->family >= CHIP_RV515) {
1131 if (p->rdev->hyperz_filp != p->filp) {
1141 if (p->rdev->hyperz_filp != p->filp) {
1179 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1183 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1186 if (p->rdev->family >= CHIP_RV350)
1192 if (p->rdev->family == CHIP_RV530)
1247 r = r100_cs_track_check(p->rdev, track);
1262 r = r100_cs_track_check(p->rdev, track);
1269 r = r100_cs_track_check(p->rdev, track);
1276 r = r100_cs_track_check(p->rdev, track);
1283 r = r100_cs_track_check(p->rdev, track);
1290 r = r100_cs_track_check(p->rdev, track);
1297 if (p->rdev->hyperz_filp != p->filp)
1301 if (p->rdev->cmask_filp != p->filp)
1322 r100_cs_track_clear(p->rdev, track);
1333 p->rdev->config.r300.reg_safe_bm,
1334 p->rdev->config.r300.reg_safe_bm_size,
1353 void r300_set_reg_safe(struct radeon_device *rdev)
1355 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1356 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1359 void r300_mc_program(struct radeon_device *rdev)
1364 r = r100_debugfs_mc_info_init(rdev);
1366 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1370 r100_mc_stop(rdev, &save);
1371 if (rdev->flags & RADEON_IS_AGP) {
1373 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1374 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1375 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1377 upper_32_bits(rdev->mc.agp_base) & 0xff);
1384 if (r300_mc_wait_for_idle(rdev))
1388 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1389 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1390 r100_mc_resume(rdev, &save);
1393 void r300_clock_startup(struct radeon_device *rdev)
1398 radeon_legacy_set_clock_gating(rdev, 1);
1402 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1407 static int r300_startup(struct radeon_device *rdev)
1412 r100_set_common_regs(rdev);
1414 r300_mc_program(rdev);
1416 r300_clock_startup(rdev);
1418 r300_gpu_init(rdev);
1421 if (rdev->flags & RADEON_IS_PCIE) {
1422 r = rv370_pcie_gart_enable(rdev);
1427 if (rdev->family == CHIP_R300 ||
1428 rdev->family == CHIP_R350 ||
1429 rdev->family == CHIP_RV350)
1430 r100_enable_bm(rdev);
1432 if (rdev->flags & RADEON_IS_PCI) {
1433 r = r100_pci_gart_enable(rdev);
1439 r = radeon_wb_init(rdev);
1443 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1445 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1450 if (!rdev->irq.installed) {
1451 r = radeon_irq_kms_init(rdev);
1456 r100_irq_set(rdev);
1457 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1459 r = r100_cp_init(rdev, 1024 * 1024);
1461 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1465 r = radeon_ib_pool_init(rdev);
1467 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1474 int r300_resume(struct radeon_device *rdev)
1479 if (rdev->flags & RADEON_IS_PCIE)
1480 rv370_pcie_gart_disable(rdev);
1481 if (rdev->flags & RADEON_IS_PCI)
1482 r100_pci_gart_disable(rdev);
1484 r300_clock_startup(rdev);
1486 if (radeon_asic_reset(rdev)) {
1487 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1492 radeon_combios_asic_init(rdev->ddev);
1494 r300_clock_startup(rdev);
1496 radeon_surface_init(rdev);
1498 rdev->accel_working = true;
1499 r = r300_startup(rdev);
1501 rdev->accel_working = false;
1506 int r300_suspend(struct radeon_device *rdev)
1508 radeon_pm_suspend(rdev);
1509 r100_cp_disable(rdev);
1510 radeon_wb_disable(rdev);
1511 r100_irq_disable(rdev);
1512 if (rdev->flags & RADEON_IS_PCIE)
1513 rv370_pcie_gart_disable(rdev);
1514 if (rdev->flags & RADEON_IS_PCI)
1515 r100_pci_gart_disable(rdev);
1519 void r300_fini(struct radeon_device *rdev)
1521 radeon_pm_fini(rdev);
1522 r100_cp_fini(rdev);
1523 radeon_wb_fini(rdev);
1524 radeon_ib_pool_fini(rdev);
1525 radeon_gem_fini(rdev);
1526 if (rdev->flags & RADEON_IS_PCIE)
1527 rv370_pcie_gart_fini(rdev);
1528 if (rdev->flags & RADEON_IS_PCI)
1529 r100_pci_gart_fini(rdev);
1530 radeon_agp_fini(rdev);
1531 radeon_irq_kms_fini(rdev);
1532 radeon_fence_driver_fini(rdev);
1533 radeon_bo_fini(rdev);
1534 radeon_atombios_fini(rdev);
1535 kfree(rdev->bios);
1536 rdev->bios = NULL;
1539 int r300_init(struct radeon_device *rdev)
1544 r100_vga_render_disable(rdev);
1546 radeon_scratch_init(rdev);
1548 radeon_surface_init(rdev);
1551 r100_restore_sanity(rdev);
1553 if (!radeon_get_bios(rdev)) {
1554 if (ASIC_IS_AVIVO(rdev))
1557 if (rdev->is_atom_bios) {
1558 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1561 r = radeon_combios_init(rdev);
1566 if (radeon_asic_reset(rdev)) {
1567 dev_warn(rdev->dev,
1573 if (radeon_boot_test_post_card(rdev) == false)
1576 r300_errata(rdev);
1578 radeon_get_clock_info(rdev->ddev);
1580 if (rdev->flags & RADEON_IS_AGP) {
1581 r = radeon_agp_init(rdev);
1583 radeon_agp_disable(rdev);
1587 r300_mc_init(rdev);
1589 r = radeon_fence_driver_init(rdev);
1593 r = radeon_bo_init(rdev);
1596 if (rdev->flags & RADEON_IS_PCIE) {
1597 r = rv370_pcie_gart_init(rdev);
1601 if (rdev->flags & RADEON_IS_PCI) {
1602 r = r100_pci_gart_init(rdev);
1606 r300_set_reg_safe(rdev);
1609 radeon_pm_init(rdev);
1611 rdev->accel_working = true;
1612 r = r300_startup(rdev);
1615 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1616 r100_cp_fini(rdev);
1617 radeon_wb_fini(rdev);
1618 radeon_ib_pool_fini(rdev);
1619 radeon_irq_kms_fini(rdev);
1620 if (rdev->flags & RADEON_IS_PCIE)
1621 rv370_pcie_gart_fini(rdev);
1622 if (rdev->flags & RADEON_IS_PCI)
1623 r100_pci_gart_fini(rdev);
1624 radeon_agp_fini(rdev);
1625 rdev->accel_working = false;