Lines Matching defs:rdev
50 void r420_pm_init_profile(struct radeon_device *rdev)
53 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
54 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
55 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
56 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
58 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
59 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
60 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
61 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
63 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
64 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
65 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
66 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
68 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
69 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
70 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
71 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
73 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
74 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
75 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
76 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
78 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
79 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
80 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
81 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
83 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
84 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
85 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
86 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
89 static void r420_set_reg_safe(struct radeon_device *rdev)
91 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
92 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
95 void r420_pipes_init(struct radeon_device *rdev)
105 if (r100_gui_wait_for_idle(rdev)) {
113 if ((rdev->pdev->device == 0x5e4c) ||
114 (rdev->pdev->device == 0x5e4f))
117 rdev->num_gb_pipes = num_pipes;
141 if (r100_gui_wait_for_idle(rdev)) {
153 if (r100_gui_wait_for_idle(rdev)) {
157 if (rdev->family == CHIP_RV530) {
160 rdev->num_z_pipes = 2;
162 rdev->num_z_pipes = 1;
164 rdev->num_z_pipes = 1;
167 rdev->num_gb_pipes, rdev->num_z_pipes);
170 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
175 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
178 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
182 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
186 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
190 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
193 static void r420_debugfs(struct radeon_device *rdev)
195 if (r100_debugfs_rbbm_init(rdev)) {
198 if (r420_debugfs_pipes_info_init(rdev)) {
203 static void r420_clock_resume(struct radeon_device *rdev)
208 radeon_atom_set_clock_gating(rdev, 1);
211 if (rdev->family == CHIP_R420)
216 static void r420_cp_errata_init(struct radeon_device *rdev)
219 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
227 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
228 r = radeon_ring_lock(rdev, ring, 8);
231 radeon_ring_write(ring, rdev->config.r300.resync_scratch);
233 radeon_ring_unlock_commit(rdev, ring, false);
236 static void r420_cp_errata_fini(struct radeon_device *rdev)
239 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
244 r = radeon_ring_lock(rdev, ring, 8);
248 radeon_ring_unlock_commit(rdev, ring, false);
249 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
252 static int r420_startup(struct radeon_device *rdev)
257 r100_set_common_regs(rdev);
259 r300_mc_program(rdev);
261 r420_clock_resume(rdev);
264 if (rdev->flags & RADEON_IS_PCIE) {
265 r = rv370_pcie_gart_enable(rdev);
269 if (rdev->flags & RADEON_IS_PCI) {
270 r = r100_pci_gart_enable(rdev);
274 r420_pipes_init(rdev);
277 r = radeon_wb_init(rdev);
281 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
283 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
288 if (!rdev->irq.installed) {
289 r = radeon_irq_kms_init(rdev);
294 r100_irq_set(rdev);
295 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
297 r = r100_cp_init(rdev, 1024 * 1024);
299 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
302 r420_cp_errata_init(rdev);
304 r = radeon_ib_pool_init(rdev);
306 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
313 int r420_resume(struct radeon_device *rdev)
318 if (rdev->flags & RADEON_IS_PCIE)
319 rv370_pcie_gart_disable(rdev);
320 if (rdev->flags & RADEON_IS_PCI)
321 r100_pci_gart_disable(rdev);
323 r420_clock_resume(rdev);
325 if (radeon_asic_reset(rdev)) {
326 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
331 if (rdev->is_atom_bios) {
332 atom_asic_init(rdev->mode_info.atom_context);
334 radeon_combios_asic_init(rdev->ddev);
337 r420_clock_resume(rdev);
339 radeon_surface_init(rdev);
341 rdev->accel_working = true;
342 r = r420_startup(rdev);
344 rdev->accel_working = false;
349 int r420_suspend(struct radeon_device *rdev)
351 radeon_pm_suspend(rdev);
352 r420_cp_errata_fini(rdev);
353 r100_cp_disable(rdev);
354 radeon_wb_disable(rdev);
355 r100_irq_disable(rdev);
356 if (rdev->flags & RADEON_IS_PCIE)
357 rv370_pcie_gart_disable(rdev);
358 if (rdev->flags & RADEON_IS_PCI)
359 r100_pci_gart_disable(rdev);
363 void r420_fini(struct radeon_device *rdev)
365 radeon_pm_fini(rdev);
366 r100_cp_fini(rdev);
367 radeon_wb_fini(rdev);
368 radeon_ib_pool_fini(rdev);
369 radeon_gem_fini(rdev);
370 if (rdev->flags & RADEON_IS_PCIE)
371 rv370_pcie_gart_fini(rdev);
372 if (rdev->flags & RADEON_IS_PCI)
373 r100_pci_gart_fini(rdev);
374 radeon_agp_fini(rdev);
375 radeon_irq_kms_fini(rdev);
376 radeon_fence_driver_fini(rdev);
377 radeon_bo_fini(rdev);
378 if (rdev->is_atom_bios) {
379 radeon_atombios_fini(rdev);
381 radeon_combios_fini(rdev);
383 kfree(rdev->bios);
384 rdev->bios = NULL;
387 int r420_init(struct radeon_device *rdev)
392 radeon_scratch_init(rdev);
394 radeon_surface_init(rdev);
397 r100_restore_sanity(rdev);
399 if (!radeon_get_bios(rdev)) {
400 if (ASIC_IS_AVIVO(rdev))
403 if (rdev->is_atom_bios) {
404 r = radeon_atombios_init(rdev);
409 r = radeon_combios_init(rdev);
415 if (radeon_asic_reset(rdev)) {
416 dev_warn(rdev->dev,
422 if (radeon_boot_test_post_card(rdev) == false)
426 radeon_get_clock_info(rdev->ddev);
428 if (rdev->flags & RADEON_IS_AGP) {
429 r = radeon_agp_init(rdev);
431 radeon_agp_disable(rdev);
435 r300_mc_init(rdev);
436 r420_debugfs(rdev);
438 r = radeon_fence_driver_init(rdev);
443 r = radeon_bo_init(rdev);
447 if (rdev->family == CHIP_R420)
448 r100_enable_bm(rdev);
450 if (rdev->flags & RADEON_IS_PCIE) {
451 r = rv370_pcie_gart_init(rdev);
455 if (rdev->flags & RADEON_IS_PCI) {
456 r = r100_pci_gart_init(rdev);
460 r420_set_reg_safe(rdev);
463 radeon_pm_init(rdev);
465 rdev->accel_working = true;
466 r = r420_startup(rdev);
469 dev_err(rdev->dev, "Disabling GPU acceleration\n");
470 r100_cp_fini(rdev);
471 radeon_wb_fini(rdev);
472 radeon_ib_pool_fini(rdev);
473 radeon_irq_kms_fini(rdev);
474 if (rdev->flags & RADEON_IS_PCIE)
475 rv370_pcie_gart_fini(rdev);
476 if (rdev->flags & RADEON_IS_PCI)
477 r100_pci_gart_fini(rdev);
478 radeon_agp_fini(rdev);
479 rdev->accel_working = false;
492 struct radeon_device *rdev = dev->dev_private;
509 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
512 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);