Lines Matching refs:WREG32
133 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
144 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
145 WREG32(R600_RCU_DATA, (v));
155 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
166 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
167 WREG32(R600_UVD_CTX_DATA, (v));
353 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
880 WREG32(DC_HPD1_INT_CONTROL, tmp);
888 WREG32(DC_HPD2_INT_CONTROL, tmp);
896 WREG32(DC_HPD3_INT_CONTROL, tmp);
904 WREG32(DC_HPD4_INT_CONTROL, tmp);
912 WREG32(DC_HPD5_INT_CONTROL, tmp);
921 WREG32(DC_HPD6_INT_CONTROL, tmp);
934 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
942 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
950 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
982 WREG32(DC_HPD1_CONTROL, tmp);
985 WREG32(DC_HPD2_CONTROL, tmp);
988 WREG32(DC_HPD3_CONTROL, tmp);
991 WREG32(DC_HPD4_CONTROL, tmp);
995 WREG32(DC_HPD5_CONTROL, tmp);
998 WREG32(DC_HPD6_CONTROL, tmp);
1006 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
1009 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
1012 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
1036 WREG32(DC_HPD1_CONTROL, 0);
1039 WREG32(DC_HPD2_CONTROL, 0);
1042 WREG32(DC_HPD3_CONTROL, 0);
1045 WREG32(DC_HPD4_CONTROL, 0);
1049 WREG32(DC_HPD5_CONTROL, 0);
1052 WREG32(DC_HPD6_CONTROL, 0);
1060 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
1063 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
1066 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
1118 WREG32(HDP_DEBUG1, 0);
1121 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1123 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
1124 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
1125 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1176 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1179 WREG32(VM_L2_CNTL2, 0);
1180 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1186 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1187 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1188 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1189 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1190 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1191 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1192 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1193 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1194 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1195 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1196 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1197 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1198 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1199 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1200 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1201 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1202 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1203 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1204 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1205 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1207 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1210 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1227 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1230 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1232 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1236 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1237 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1238 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1239 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1240 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1241 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1242 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1243 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1244 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1245 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1246 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1247 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1248 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1249 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1250 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1251 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1268 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1271 WREG32(VM_L2_CNTL2, 0);
1272 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1278 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1279 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1280 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1281 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1282 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1283 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1284 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1285 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1286 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1287 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1288 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1289 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1290 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1291 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1293 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1317 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1319 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1329 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1331 WREG32(R_0028FC_MC_DATA, v);
1332 WREG32(R_0028F8_MC_INDEX, 0x7F);
1344 WREG32((0x2c14 + j), 0x00000000);
1345 WREG32((0x2c18 + j), 0x00000000);
1346 WREG32((0x2c1c + j), 0x00000000);
1347 WREG32((0x2c20 + j), 0x00000000);
1348 WREG32((0x2c24 + j), 0x00000000);
1350 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1357 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1362 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1364 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1368 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1370 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1374 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1375 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1377 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1380 WREG32(MC_VM_FB_LOCATION, tmp);
1381 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1382 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1383 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1385 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1386 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1387 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1389 WREG32(MC_VM_AGP_BASE, 0);
1390 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1391 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1597 WREG32(R600_BIOS_3_SCRATCH, tmp);
1733 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1735 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1738 WREG32(RLC_CNTL, 0);
1744 WREG32(DMA_RB_CNTL, tmp);
1821 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1827 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1835 WREG32(SRBM_SOFT_RESET, tmp);
1841 WREG32(SRBM_SOFT_RESET, tmp);
1865 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1867 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1870 WREG32(RLC_CNTL, 0);
1875 WREG32(DMA_RB_CNTL, tmp);
1893 WREG32(BUS_CNTL, tmp);
1903 WREG32(SRBM_SOFT_RESET, tmp);
1905 WREG32(SRBM_SOFT_RESET, 0);
2110 WREG32((0x2c14 + j), 0x00000000);
2111 WREG32((0x2c18 + j), 0x00000000);
2112 WREG32((0x2c1c + j), 0x00000000);
2113 WREG32((0x2c20 + j), 0x00000000);
2114 WREG32((0x2c24 + j), 0x00000000);
2117 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
2174 WREG32(GB_TILING_CONFIG, tiling_config);
2175 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
2176 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
2177 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
2180 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
2181 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
2184 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
2185 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
2187 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
2191 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
2197 WREG32(SX_DEBUG_1, tmp);
2205 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
2207 WREG32(DB_DEBUG, 0);
2209 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
2212 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2213 WREG32(VGT_NUM_INSTANCES, 0);
2215 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
2216 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
2232 WREG32(SQ_MS_FIFO_SIZES, tmp);
2314 WREG32(SQ_CONFIG, sq_config);
2315 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2316 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2317 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2318 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2319 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2325 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2327 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2331 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2333 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2337 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2341 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2346 WREG32(VGT_STRMOUT_EN, 0);
2364 WREG32(VGT_ES_PER_GS, 128);
2365 WREG32(VGT_GS_PER_ES, tmp);
2366 WREG32(VGT_GS_PER_VS, 2);
2367 WREG32(VGT_GS_VERTEX_REUSE, 16);
2370 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2371 WREG32(VGT_STRMOUT_EN, 0);
2372 WREG32(SX_MISC, 0);
2373 WREG32(PA_SC_MODE_CNTL, 0);
2374 WREG32(PA_SC_AA_CONFIG, 0);
2375 WREG32(PA_SC_LINE_STIPPLE, 0);
2376 WREG32(SPI_INPUT_Z, 0);
2377 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2378 WREG32(CB_COLOR7_FRAG, 0);
2381 WREG32(CB_COLOR0_BASE, 0);
2382 WREG32(CB_COLOR1_BASE, 0);
2383 WREG32(CB_COLOR2_BASE, 0);
2384 WREG32(CB_COLOR3_BASE, 0);
2385 WREG32(CB_COLOR4_BASE, 0);
2386 WREG32(CB_COLOR5_BASE, 0);
2387 WREG32(CB_COLOR6_BASE, 0);
2388 WREG32(CB_COLOR7_BASE, 0);
2389 WREG32(CB_COLOR7_FRAG, 0);
2409 WREG32(TC_CNTL, tmp);
2412 WREG32(HDP_HOST_PATH_CNTL, tmp);
2416 WREG32(ARB_POP, tmp);
2418 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2419 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2421 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
2422 WREG32(VC_ENHANCE, 0);
2435 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2447 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2449 WREG32(PCIE_PORT_DATA, (v));
2461 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
2462 WREG32(SCRATCH_UMSK, 0);
2672 WREG32(R600_CP_RB_WPTR, ring->wptr);
2686 WREG32(CP_RB_CNTL,
2693 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2696 WREG32(GRBM_SOFT_RESET, 0);
2698 WREG32(CP_ME_RAM_WADDR, 0);
2701 WREG32(CP_ME_RAM_WADDR, 0);
2703 WREG32(CP_ME_RAM_DATA,
2707 WREG32(CP_PFP_UCODE_ADDR, 0);
2709 WREG32(CP_PFP_UCODE_DATA,
2712 WREG32(CP_PFP_UCODE_ADDR, 0);
2713 WREG32(CP_ME_RAM_WADDR, 0);
2714 WREG32(CP_ME_RAM_RADDR, 0);
2744 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2756 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2759 WREG32(GRBM_SOFT_RESET, 0);
2767 WREG32(CP_RB_CNTL, tmp);
2768 WREG32(CP_SEM_WAIT_TIMER, 0x0);
2771 WREG32(CP_RB_WPTR_DELAY, 0);
2774 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2775 WREG32(CP_RB_RPTR_WR, 0);
2777 WREG32(CP_RB_WPTR, ring->wptr);
2780 WREG32(CP_RB_RPTR_ADDR,
2782 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2783 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2786 WREG32(SCRATCH_UMSK, 0xff);
2789 WREG32(SCRATCH_UMSK, 0);
2793 WREG32(CP_RB_CNTL, tmp);
2795 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2796 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2867 WREG32(scratch, 0xCAFEDEAD);
3233 WREG32(CONFIG_CNTL, temp);
3445 WREG32(scratch, 0xCAFEDEAD);
3572 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3575 WREG32(SRBM_SOFT_RESET, 0);
3579 WREG32(RLC_CNTL, 0);
3584 WREG32(RLC_CNTL, RLC_ENABLE);
3597 WREG32(RLC_HB_CNTL, 0);
3599 WREG32(RLC_HB_BASE, 0);
3600 WREG32(RLC_HB_RPTR, 0);
3601 WREG32(RLC_HB_WPTR, 0);
3602 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3603 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3604 WREG32(RLC_MC_CNTL, 0);
3605 WREG32(RLC_UCODE_CNTL, 0);
3610 WREG32(RLC_UCODE_ADDR, i);
3611 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3615 WREG32(RLC_UCODE_ADDR, i);
3616 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3619 WREG32(RLC_UCODE_ADDR, 0);
3633 WREG32(IH_CNTL, ih_cntl);
3634 WREG32(IH_RB_CNTL, ih_rb_cntl);
3645 WREG32(IH_RB_CNTL, ih_rb_cntl);
3646 WREG32(IH_CNTL, ih_cntl);
3648 WREG32(IH_RB_RPTR, 0);
3649 WREG32(IH_RB_WPTR, 0);
3658 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3660 WREG32(DMA_CNTL, tmp);
3661 WREG32(GRBM_INT_CNTL, 0);
3662 WREG32(DxMODE_INT_MASK, 0);
3663 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3664 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3666 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3667 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3669 WREG32(DC_HPD1_INT_CONTROL, tmp);
3671 WREG32(DC_HPD2_INT_CONTROL, tmp);
3673 WREG32(DC_HPD3_INT_CONTROL, tmp);
3675 WREG32(DC_HPD4_INT_CONTROL, tmp);
3678 WREG32(DC_HPD5_INT_CONTROL, tmp);
3680 WREG32(DC_HPD6_INT_CONTROL, tmp);
3682 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3684 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3687 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3689 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3692 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3693 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3695 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3697 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3699 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3701 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3703 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3733 WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8);
3741 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3743 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3754 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3755 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3757 WREG32(IH_RB_CNTL, ih_rb_cntl);
3760 WREG32(IH_RB_RPTR, 0);
3761 WREG32(IH_RB_WPTR, 0);
3768 WREG32(IH_CNTL, ih_cntl);
3909 WREG32(CP_INT_CNTL, cp_int_cntl);
3910 WREG32(DMA_CNTL, dma_cntl);
3911 WREG32(DxMODE_INT_MASK, mode_int);
3912 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3913 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3914 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3916 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3917 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3918 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3919 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3921 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3922 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3923 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3924 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3926 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3927 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3930 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3931 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3932 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3933 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3934 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3937 WREG32(CG_THERMAL_INT, thermal_int);
3939 WREG32(RV770_CG_THERMAL_INT, thermal_int);
3974 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3976 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3978 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3980 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3982 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3984 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3989 WREG32(DC_HPD1_INT_CONTROL, tmp);
3993 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
4000 WREG32(DC_HPD2_INT_CONTROL, tmp);
4004 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
4011 WREG32(DC_HPD3_INT_CONTROL, tmp);
4015 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
4021 WREG32(DC_HPD4_INT_CONTROL, tmp);
4027 WREG32(DC_HPD5_INT_CONTROL, tmp);
4032 WREG32(DC_HPD6_INT_CONTROL, tmp);
4037 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
4042 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
4048 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
4054 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
4058 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
4093 WREG32(IH_RB_CNTL, tmp);
4372 WREG32(IH_RB_RPTR, rptr);
4446 WREG32(HDP_DEBUG1, 0);
4449 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4610 WREG32(MM_CFGREGS_CNTL, 0x8);
4612 WREG32(MM_CFGREGS_CNTL, 0);
4626 WREG32(0x541c, tmp | 0x8);
4627 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4632 WREG32(MM_CFGREGS_CNTL, 0);
4674 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
Indexes created Tue Oct 21 08:09:48 GMT 2025