Lines Matching refs:r600
115 /* r600,rv610,rv630,rv620,rv635,rv670 */
1101 * R600 PCIE GART
1131 pr_warn("[drm] r600 flush TLB failed\n");
1151 WARN(1, "R600 PCIE GART already initialized\n");
1356 /* Lockout access through VGA aperture (doesn't exist before R600) */
2038 rdev->config.r600.tiling_group_size = 256;
2041 rdev->config.r600.max_pipes = 4;
2042 rdev->config.r600.max_tile_pipes = 8;
2043 rdev->config.r600.max_simds = 4;
2044 rdev->config.r600.max_backends = 4;
2045 rdev->config.r600.max_gprs = 256;
2046 rdev->config.r600.max_threads = 192;
2047 rdev->config.r600.max_stack_entries = 256;
2048 rdev->config.r600.max_hw_contexts = 8;
2049 rdev->config.r600.max_gs_threads = 16;
2050 rdev->config.r600.sx_max_export_size = 128;
2051 rdev->config.r600.sx_max_export_pos_size = 16;
2052 rdev->config.r600.sx_max_export_smx_size = 128;
2053 rdev->config.r600.sq_num_cf_insts = 2;
2057 rdev->config.r600.max_pipes = 2;
2058 rdev->config.r600.max_tile_pipes = 2;
2059 rdev->config.r600.max_simds = 3;
2060 rdev->config.r600.max_backends = 1;
2061 rdev->config.r600.max_gprs = 128;
2062 rdev->config.r600.max_threads = 192;
2063 rdev->config.r600
2064 rdev->config.r600.max_hw_contexts = 8;
2065 rdev->config.r600.max_gs_threads = 4;
2066 rdev->config.r600.sx_max_export_size = 128;
2067 rdev->config.r600.sx_max_export_pos_size = 16;
2068 rdev->config.r600.sx_max_export_smx_size = 128;
2069 rdev->config.r600.sq_num_cf_insts = 2;
2075 rdev->config.r600.max_pipes = 1;
2076 rdev->config.r600.max_tile_pipes = 1;
2077 rdev->config.r600.max_simds = 2;
2078 rdev->config.r600.max_backends = 1;
2079 rdev->config.r600.max_gprs = 128;
2080 rdev->config.r600.max_threads = 192;
2081 rdev->config.r600.max_stack_entries = 128;
2082 rdev->config.r600.max_hw_contexts = 4;
2083 rdev->config.r600.max_gs_threads = 4;
2084 rdev->config.r600.sx_max_export_size = 128;
2085 rdev->config.r600.sx_max_export_pos_size = 16;
2086 rdev->config.r600.sx_max_export_smx_size = 128;
2087 rdev->config.r600.sq_num_cf_insts = 1;
2090 rdev->config.r600.max_pipes = 4;
2091 rdev->config.r600.max_tile_pipes = 4;
2092 rdev->config.r600.max_simds = 4;
2093 rdev->config.r600.max_backends = 4;
2094 rdev->config.r600.max_gprs = 192;
2095 rdev->config.r600.max_threads = 192;
2096 rdev->config.r600.max_stack_entries = 256;
2097 rdev->config.r600.max_hw_contexts = 8;
2098 rdev->config.r600.max_gs_threads = 16;
2099 rdev->config.r600.sx_max_export_size = 128;
2100 rdev->config.r600.sx_max_export_pos_size = 16;
2101 rdev->config.r600.sx_max_export_smx_size = 128;
2102 rdev->config.r600.sq_num_cf_insts = 2;
2122 switch (rdev->config.r600.max_tile_pipes) {
2138 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
2139 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2154 tmp = rdev->config.r600.max_simds -
2156 rdev->config.r600.active_simds = tmp;
2160 for (i = 0; i < rdev->config.r600.max_backends; i++)
2164 for (i = 0; i < rdev->config.r600.max_backends; i++)
2168 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
2171 rdev->config.r600.backend_map = tmp;
2173 rdev->config.r600.tile_config = tiling_config;
2347 tmp = rdev->config.r600.max_pipes * 16;
2479 chip_name = "R600";
2480 rlc_chip_name = "R600";
2484 rlc_chip_name = "R600";
2488 rlc_chip_name = "R600";
2492 rlc_chip_name = "R600";
2496 rlc_chip_name = "R600";
2500 rlc_chip_name = "R600";
2505 rlc_chip_name = "R600";
2736 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
3240 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3253 DRM_ERROR("r600 startup failed on resume\n");
3297 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3953 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3954 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3955 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3957 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3958 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3960 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3961 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3964 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3965 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3966 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3967 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3968 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3970 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3971 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3973 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3975 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3977 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3979 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3981 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3983 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3985 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3996 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
4007 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
4018 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
4024 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
4029 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
4034 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
4039 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
4045 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4050 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4098 /* r600 IV Ring
4124 * Note, these are based on r600 and may need to be
4171 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT))
4188 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
4193 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT))
4196 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
4208 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT))
4225 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
4230 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT))
4233 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
4255 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT))
4258 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
4263 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT))
4266 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
4271 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT))
4274 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
4279 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT))
4282 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
4287 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT))
4290 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
4295 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT))
4298 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
4311 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG))
4314 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4320 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG))
4323 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
Indexes created Thu Oct 16 14:10:15 GMT 2025