Lines Matching refs:RREG32
68 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
78 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
79 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
102 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
126 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
143 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
159 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
237 tmp = RREG32(voltage->gpio.reg);
246 tmp = RREG32(voltage->gpio.reg);
332 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
350 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
365 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
370 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
388 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
396 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
467 status = RREG32(R_000E40_RBBM_STATUS);
473 status = RREG32(R_000E40_RBBM_STATUS);
477 tmp = RREG32(RADEON_CP_RB_CNTL);
489 RREG32(R_0000F0_RBBM_SOFT_RESET);
493 status = RREG32(R_000E40_RBBM_STATUS);
497 RREG32(R_0000F0_RBBM_SOFT_RESET);
501 status = RREG32(R_000E40_RBBM_STATUS);
505 RREG32(R_0000F0_RBBM_SOFT_RESET);
509 status = RREG32(R_000E40_RBBM_STATUS);
574 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
687 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
689 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
693 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
731 RREG32(R_000040_GEN_INT_CNTL);
738 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
743 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
753 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
758 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
767 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
770 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
785 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
870 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
885 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
887 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
918 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
950 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
951 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
969 r = RREG32(R_000074_MC_IND_DATA);
1056 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1090 RREG32(R_000E40_RBBM_STATUS),
1091 RREG32(R_0007C0_CP_STAT));
1165 RREG32(R_000E40_RBBM_STATUS),
1166 RREG32(R_0007C0_CP_STAT));
Indexes created Thu Nov 06 07:09:58 GMT 2025