Lines Matching refs:rdev
57 static void rs600_gpu_init(struct radeon_device *rdev);
58 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
66 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
74 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
90 * @rdev: radeon_device pointer
95 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
99 if (crtc >= rdev->num_crtc)
108 while (avivo_is_in_vblank(rdev, crtc)) {
110 if (!avivo_is_counter_moving(rdev, crtc))
115 while (!avivo_is_in_vblank(rdev, crtc)) {
117 if (!avivo_is_counter_moving(rdev, crtc))
123 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
125 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
142 for (i = 0; i < rdev->usec_timeout; i++) {
154 bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id)
156 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
166 struct radeon_device *rdev = dev->dev_private;
227 void rs600_pm_misc(struct radeon_device *rdev)
229 int requested_index = rdev->pm.requested_power_state_index;
230 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
256 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
310 if ((rdev->flags & RADEON_IS_PCIE) &&
311 !(rdev->flags & RADEON_IS_IGP) &&
312 rdev->asic->pm.set_pcie_lanes &&
314 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
315 radeon_set_pcie_lanes(rdev,
321 void rs600_pm_prepare(struct radeon_device *rdev)
323 struct drm_device *ddev = rdev->ddev;
339 void rs600_pm_finish(struct radeon_device *rdev)
341 struct drm_device *ddev = rdev->ddev;
358 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
380 void rs600_hpd_set_polarity(struct radeon_device *rdev,
384 bool connected = rs600_hpd_sense(rdev, hpd);
408 void rs600_hpd_init(struct radeon_device *rdev)
410 struct drm_device *dev = rdev->ddev;
430 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
432 radeon_irq_kms_enable_hpd(rdev, enable);
435 void rs600_hpd_fini(struct radeon_device *rdev)
437 struct drm_device *dev = rdev->ddev;
458 radeon_irq_kms_disable_hpd(rdev, disable);
461 int rs600_asic_reset(struct radeon_device *rdev, bool hard)
472 rv515_mc_stop(rdev, &save);
474 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
482 pci_save_state(rdev->pdev);
484 pci_clear_master(rdev->pdev);
494 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
502 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
510 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
512 pci_restore_state(rdev->pdev);
515 dev_err(rdev->dev, "failed to reset GPU\n");
518 dev_info(rdev->dev, "GPU reset succeed\n");
519 rv515_mc_resume(rdev, &save);
526 void rs600_gart_tlb_flush(struct radeon_device *rdev)
544 static int rs600_gart_init(struct radeon_device *rdev)
548 if (rdev->gart.robj) {
553 r = radeon_gart_init(rdev);
557 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
558 return radeon_gart_table_vram_alloc(rdev);
561 static int rs600_gart_enable(struct radeon_device *rdev)
566 if (rdev->gart.robj == NULL) {
567 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
570 r = radeon_gart_table_vram_pin(rdev);
603 rdev->gart.table_addr);
604 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
605 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
609 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
610 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
617 rs600_gart_tlb_flush(rdev);
619 (unsigned)(rdev->mc.gtt_size >> 20),
620 (unsigned long long)rdev->gart.table_addr);
621 rdev->gart.ready = true;
625 static void rs600_gart_disable(struct radeon_device *rdev)
633 radeon_gart_table_vram_unpin(rdev);
636 static void rs600_gart_fini(struct radeon_device *rdev)
638 radeon_gart_fini(rdev);
639 rs600_gart_disable(rdev);
640 radeon_gart_table_vram_free(rdev);
671 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
674 void __iomem *ptr = (void *)rdev->gart.ptr;
683 int rs600_irq_set(struct radeon_device *rdev)
692 if (ASIC_IS_DCE2(rdev))
698 if (!rdev->irq.installed) {
703 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
706 if (rdev->irq.crtc_vblank_int[0] ||
707 atomic_read(&rdev->irq.pflip[0])) {
710 if (rdev->irq.crtc_vblank_int[1] ||
711 atomic_read(&rdev->irq.pflip[1])) {
714 if (rdev->irq.hpd[0]) {
717 if (rdev->irq.hpd[1]) {
720 if (rdev->irq.afmt[0]) {
727 if (ASIC_IS_DCE2(rdev))
736 static inline u32 rs600_irq_ack(struct radeon_device *rdev)
743 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
744 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
748 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
752 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
757 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
763 rdev->irq.stat_regs.r500.disp_int = 0;
766 if (ASIC_IS_DCE2(rdev)) {
767 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
769 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
775 rdev->irq.stat_regs.r500.hdmi0_status = 0;
783 void rs600_irq_disable(struct radeon_device *rdev)
792 rs600_irq_ack(rdev);
795 int rs600_irq_process(struct radeon_device *rdev)
801 status = rs600_irq_ack(rdev);
803 !rdev->irq.stat_regs.r500.disp_int &&
804 !rdev->irq.stat_regs.r500.hdmi0_status) {
808 rdev->irq.stat_regs.r500.disp_int ||
809 rdev->irq.stat_regs.r500.hdmi0_status) {
812 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
815 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
816 if (rdev->irq.crtc_vblank_int[0]) {
817 drm_handle_vblank(rdev->ddev, 0);
819 spin_lock(&rdev->irq.vblank_lock);
820 rdev->pm.vblank_sync = true;
821 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock);
822 spin_unlock(&rdev->irq.vblank_lock);
824 rdev->pm.vblank_sync = true;
825 wake_up(&rdev->irq.vblank_queue);
828 if (atomic_read(&rdev->irq.pflip[0]))
829 radeon_crtc_handle_vblank(rdev, 0);
831 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
832 if (rdev->irq.crtc_vblank_int[1]) {
833 drm_handle_vblank(rdev->ddev, 1);
835 spin_lock(&rdev->irq.vblank_lock);
836 rdev->pm.vblank_sync = true;
837 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock);
838 spin_unlock(&rdev->irq.vblank_lock);
840 rdev->pm.vblank_sync = true;
841 wake_up(&rdev->irq.vblank_queue);
844 if (atomic_read(&rdev->irq.pflip[1]))
845 radeon_crtc_handle_vblank(rdev, 1);
847 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
851 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
855 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
859 status = rs600_irq_ack(rdev);
862 schedule_delayed_work(&rdev->hotplug_work, 0);
864 schedule_work(&rdev->audio_work);
865 if (rdev->msi_enabled) {
866 switch (rdev->family) {
882 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
890 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
894 for (i = 0; i < rdev->usec_timeout; i++) {
902 static void rs600_gpu_init(struct radeon_device *rdev)
904 r420_pipes_init(rdev);
906 if (rs600_mc_wait_for_idle(rdev))
907 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
910 static void rs600_mc_init(struct radeon_device *rdev)
914 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
915 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
916 rdev->mc.vram_is_ddr = true;
917 rdev->mc.vram_width = 128;
918 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
919 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
920 rdev->mc.visible_vram_size = rdev->mc.aper_size;
921 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
924 radeon_vram_location(rdev, &rdev->mc, base);
925 rdev->mc.gtt_base_align = 0;
926 radeon_gtt_location(rdev, &rdev->mc);
927 radeon_update_bandwidth_info(rdev);
930 void rs600_bandwidth_update(struct radeon_device *rdev)
937 if (!rdev->mode_info.mode_config_initialized)
940 radeon_update_display_priority(rdev);
942 if (rdev->mode_info.crtcs[0]->base.enabled)
943 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
944 if (rdev->mode_info.crtcs[1]->base.enabled)
945 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
947 rs690_line_buffer_adjust(rdev, mode0, mode1);
949 if (rdev->disp_priority == 2) {
961 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
966 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
970 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
974 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
978 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
982 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
985 static void rs600_debugfs(struct radeon_device *rdev)
987 if (r100_debugfs_rbbm_init(rdev))
991 void rs600_set_safe_registers(struct radeon_device *rdev)
993 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
994 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
997 static void rs600_mc_program(struct radeon_device *rdev)
1002 rv515_mc_stop(rdev, &save);
1005 if (rs600_mc_wait_for_idle(rdev))
1006 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
1014 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
1015 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
1017 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
1019 rv515_mc_resume(rdev, &save);
1022 static int rs600_startup(struct radeon_device *rdev)
1026 rs600_mc_program(rdev);
1028 rv515_clock_startup(rdev);
1030 rs600_gpu_init(rdev);
1033 r = rs600_gart_enable(rdev);
1038 r = radeon_wb_init(rdev);
1042 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1044 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1049 if (!rdev->irq.installed) {
1050 r = radeon_irq_kms_init(rdev);
1055 rs600_irq_set(rdev);
1056 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1058 r = r100_cp_init(rdev, 1024 * 1024);
1060 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1064 r = radeon_ib_pool_init(rdev);
1066 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1070 r = radeon_audio_init(rdev);
1072 dev_err(rdev->dev, "failed initializing audio\n");
1079 int rs600_resume(struct radeon_device *rdev)
1084 rs600_gart_disable(rdev);
1086 rv515_clock_startup(rdev);
1088 if (radeon_asic_reset(rdev)) {
1089 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1094 atom_asic_init(rdev->mode_info.atom_context);
1096 rv515_clock_startup(rdev);
1098 radeon_surface_init(rdev);
1100 rdev->accel_working = true;
1101 r = rs600_startup(rdev);
1103 rdev->accel_working = false;
1108 int rs600_suspend(struct radeon_device *rdev)
1110 radeon_pm_suspend(rdev);
1111 radeon_audio_fini(rdev);
1112 r100_cp_disable(rdev);
1113 radeon_wb_disable(rdev);
1114 rs600_irq_disable(rdev);
1115 rs600_gart_disable(rdev);
1119 void rs600_fini(struct radeon_device *rdev)
1121 radeon_pm_fini(rdev);
1122 radeon_audio_fini(rdev);
1123 r100_cp_fini(rdev);
1124 radeon_wb_fini(rdev);
1125 radeon_ib_pool_fini(rdev);
1126 radeon_gem_fini(rdev);
1127 rs600_gart_fini(rdev);
1128 radeon_irq_kms_fini(rdev);
1129 radeon_fence_driver_fini(rdev);
1130 radeon_bo_fini(rdev);
1131 radeon_atombios_fini(rdev);
1132 kfree(rdev->bios);
1133 rdev->bios = NULL;
1136 int rs600_init(struct radeon_device *rdev)
1141 rv515_vga_render_disable(rdev);
1143 radeon_scratch_init(rdev);
1145 radeon_surface_init(rdev);
1147 r100_restore_sanity(rdev);
1149 if (!radeon_get_bios(rdev)) {
1150 if (ASIC_IS_AVIVO(rdev))
1153 if (rdev->is_atom_bios) {
1154 r = radeon_atombios_init(rdev);
1158 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1162 if (radeon_asic_reset(rdev)) {
1163 dev_warn(rdev->dev,
1169 if (radeon_boot_test_post_card(rdev) == false)
1173 radeon_get_clock_info(rdev->ddev);
1175 rs600_mc_init(rdev);
1176 rs600_debugfs(rdev);
1178 r = radeon_fence_driver_init(rdev);
1182 r = radeon_bo_init(rdev);
1185 r = rs600_gart_init(rdev);
1188 rs600_set_safe_registers(rdev);
1191 radeon_pm_init(rdev);
1193 rdev->accel_working = true;
1194 r = rs600_startup(rdev);
1197 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1198 r100_cp_fini(rdev);
1199 radeon_wb_fini(rdev);
1200 radeon_ib_pool_fini(rdev);
1201 rs600_gart_fini(rdev);
1202 radeon_irq_kms_fini(rdev);
1203 rdev->accel_working = false;
Indexes created Wed Oct 15 07:09:58 GMT 2025