Lines Matching refs:rdev
42 int rs690_mc_wait_for_idle(struct radeon_device *rdev)
47 for (i = 0; i < rdev->usec_timeout; i++) {
57 static void rs690_gpu_init(struct radeon_device *rdev)
60 r420_pipes_init(rdev);
61 if (rs690_mc_wait_for_idle(rdev)) {
71 void rs690_pm_info(struct radeon_device *rdev)
79 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
81 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
87 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
88 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
90 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
91 else if (rdev->clock.default_mclk) {
92 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
93 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
95 rdev->pm.igp_system_mclk.full = dfixed_const(400);
96 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
97 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
101 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
102 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
104 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
105 else if (rdev->clock.default_mclk)
106 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
108 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
109 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
110 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
111 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
112 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
116 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
117 rdev->pm.igp_system_mclk.full = dfixed_const(200);
118 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
119 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
125 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
126 rdev->pm.igp_system_mclk.full = dfixed_const(200);
127 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
128 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
134 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
139 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
140 rdev->pm.igp_ht_link_width);
141 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
142 if (tmp.full < rdev->pm.max_bandwidth.full) {
144 rdev->pm.max_bandwidth.full = tmp.full;
150 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
152 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
155 static void rs690_mc_init(struct radeon_device *rdev)
161 rs400_gart_adjust_size(rdev);
162 rdev->mc.vram_is_ddr = true;
163 rdev->mc.vram_width = 128;
164 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
165 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
166 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
167 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
168 rdev->mc.visible_vram_size = rdev->mc.aper_size;
171 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
176 if (rdev->mc.igp_sideport_enabled &&
177 (rdev->mc.real_vram_size == (384 * 1024 * 1024))) {
179 rdev->mc.real_vram_size -= 128 * 1024 * 1024;
180 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
184 rdev->fastfb_working = false;
189 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
195 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
197 (unsigned long long)rdev->mc.aper_base, k8_addr);
198 rdev->mc.aper_base = (resource_size_t)k8_addr;
199 rdev->fastfb_working = true;
203 rs690_pm_info(rdev);
204 radeon_vram_location(rdev, &rdev->mc, base);
205 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
206 radeon_gtt_location(rdev, &rdev->mc);
207 radeon_update_bandwidth_info(rdev);
210 void rs690_line_buffer_adjust(struct radeon_device *rdev,
258 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
261 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
277 static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
295 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) &&
296 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
297 selected_sclk = radeon_dpm_get_sclk(rdev, low);
299 selected_sclk = rdev->pm.current_sclk;
308 core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
371 if (rdev->mc.igp_sideport_enabled) {
372 if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
373 rdev->pm.sideport_bandwidth.full)
374 max_bandwidth = rdev->pm.sideport_bandwidth;
377 b.full = dfixed_div(rdev->pm.igp_sideport_mclk, a);
381 if (max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
382 rdev->pm.k8_bandwidth.full)
383 max_bandwidth = rdev->pm.k8_bandwidth;
384 if (max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
385 rdev->pm.ht_bandwidth.full)
386 max_bandwidth = rdev->pm.ht_bandwidth;
465 static void rs690_compute_mode_priority(struct radeon_device *rdev,
528 if (rdev->disp_priority == 2) {
557 if (rdev->disp_priority == 2)
584 if (rdev->disp_priority == 2)
589 void rs690_bandwidth_update(struct radeon_device *rdev)
599 if (!rdev->mode_info.mode_config_initialized)
602 radeon_update_display_priority(rdev);
604 if (rdev->mode_info.crtcs[0]->base.enabled)
605 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
606 if (rdev->mode_info.crtcs[1]->base.enabled)
607 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
613 if ((rdev->disp_priority == 2) &&
614 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
624 rs690_line_buffer_adjust(rdev, mode0, mode1);
626 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
628 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
631 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
632 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
634 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true);
635 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true);
641 rs690_compute_mode_priority(rdev,
645 rs690_compute_mode_priority(rdev,
656 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
661 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
665 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
669 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
673 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
678 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
681 static void rs690_mc_program(struct radeon_device *rdev)
686 rv515_mc_stop(rdev, &save);
689 if (rs690_mc_wait_for_idle(rdev))
690 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
693 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
694 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
696 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
698 rv515_mc_resume(rdev, &save);
701 static int rs690_startup(struct radeon_device *rdev)
705 rs690_mc_program(rdev);
707 rv515_clock_startup(rdev);
709 rs690_gpu_init(rdev);
712 r = rs400_gart_enable(rdev);
717 r = radeon_wb_init(rdev);
721 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
723 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
728 if (!rdev->irq.installed) {
729 r = radeon_irq_kms_init(rdev);
734 rs600_irq_set(rdev);
735 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
737 r = r100_cp_init(rdev, 1024 * 1024);
739 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
743 r = radeon_ib_pool_init(rdev);
745 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
749 r = radeon_audio_init(rdev);
751 dev_err(rdev->dev, "failed initializing audio\n");
758 int rs690_resume(struct radeon_device *rdev)
763 rs400_gart_disable(rdev);
765 rv515_clock_startup(rdev);
767 if (radeon_asic_reset(rdev)) {
768 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
773 atom_asic_init(rdev->mode_info.atom_context);
775 rv515_clock_startup(rdev);
777 radeon_surface_init(rdev);
779 rdev->accel_working = true;
780 r = rs690_startup(rdev);
782 rdev->accel_working = false;
787 int rs690_suspend(struct radeon_device *rdev)
789 radeon_pm_suspend(rdev);
790 radeon_audio_fini(rdev);
791 r100_cp_disable(rdev);
792 radeon_wb_disable(rdev);
793 rs600_irq_disable(rdev);
794 rs400_gart_disable(rdev);
798 void rs690_fini(struct radeon_device *rdev)
800 radeon_pm_fini(rdev);
801 radeon_audio_fini(rdev);
802 r100_cp_fini(rdev);
803 radeon_wb_fini(rdev);
804 radeon_ib_pool_fini(rdev);
805 radeon_gem_fini(rdev);
806 rs400_gart_fini(rdev);
807 radeon_irq_kms_fini(rdev);
808 radeon_fence_driver_fini(rdev);
809 radeon_bo_fini(rdev);
810 radeon_atombios_fini(rdev);
811 kfree(rdev->bios);
812 rdev->bios = NULL;
815 int rs690_init(struct radeon_device *rdev)
820 rv515_vga_render_disable(rdev);
822 radeon_scratch_init(rdev);
824 radeon_surface_init(rdev);
826 r100_restore_sanity(rdev);
829 if (!radeon_get_bios(rdev)) {
830 if (ASIC_IS_AVIVO(rdev))
833 if (rdev->is_atom_bios) {
834 r = radeon_atombios_init(rdev);
838 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
842 if (radeon_asic_reset(rdev)) {
843 dev_warn(rdev->dev,
849 if (radeon_boot_test_post_card(rdev) == false)
853 radeon_get_clock_info(rdev->ddev);
855 rs690_mc_init(rdev);
856 rv515_debugfs(rdev);
858 r = radeon_fence_driver_init(rdev);
862 r = radeon_bo_init(rdev);
865 r = rs400_gart_init(rdev);
868 rs600_set_safe_registers(rdev);
871 radeon_pm_init(rdev);
873 rdev->accel_working = true;
874 r = rs690_startup(rdev);
877 dev_err(rdev->dev, "Disabling GPU acceleration\n");
878 r100_cp_fini(rdev);
879 radeon_wb_fini(rdev);
880 radeon_ib_pool_fini(rdev);
881 rs400_gart_fini(rdev);
882 radeon_irq_kms_fini(rdev);
883 rdev->accel_working = false;