Lines Matching refs:WREG32
821 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
824 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
827 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
828 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
830 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
831 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
833 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
835 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
848 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
915 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
918 WREG32(VM_L2_CNTL2, 0);
919 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
925 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
926 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
927 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
929 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
930 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
931 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
932 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
933 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
934 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
935 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
936 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
937 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
939 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
942 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
959 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
962 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
964 WREG32(VM_L2_CNTL2, 0);
965 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
968 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
969 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
970 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
971 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
972 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
973 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
974 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
992 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
995 WREG32(VM_L2_CNTL2, 0);
996 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1002 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1003 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1004 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1005 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1006 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1007 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1008 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1010 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1021 WREG32((0x2c14 + j), 0x00000000);
1022 WREG32((0x2c18 + j), 0x00000000);
1023 WREG32((0x2c1c + j), 0x00000000);
1024 WREG32((0x2c20 + j), 0x00000000);
1025 WREG32((0x2c24 + j), 0x00000000);
1037 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1042 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1044 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1048 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1050 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1054 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1056 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1059 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1062 WREG32(MC_VM_FB_LOCATION, tmp);
1063 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1064 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1065 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1067 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1068 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1069 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1071 WREG32(MC_VM_AGP_BASE, 0);
1072 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1073 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1092 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1093 WREG32(SCRATCH_UMSK, 0);
1106 WREG32(CP_RB_CNTL,
1113 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1116 WREG32(GRBM_SOFT_RESET, 0);
1119 WREG32(CP_PFP_UCODE_ADDR, 0);
1121 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1122 WREG32(CP_PFP_UCODE_ADDR, 0);
1125 WREG32(CP_ME_RAM_WADDR, 0);
1127 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1129 WREG32(CP_PFP_UCODE_ADDR, 0);
1130 WREG32(CP_ME_RAM_WADDR, 0);
1131 WREG32(CP_ME_RAM_RADDR, 0);
1153 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1162 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1169 WREG32(MPLL_CNTL_MODE, tmp);
1297 WREG32((0x2c14 + j), 0x00000000);
1298 WREG32((0x2c18 + j), 0x00000000);
1299 WREG32((0x2c1c + j), 0x00000000);
1300 WREG32((0x2c20 + j), 0x00000000);
1301 WREG32((0x2c24 + j), 0x00000000);
1305 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1319 WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1);
1321 WREG32(SPI_CONFIG_CNTL, 0);
1384 WREG32(GB_TILING_CONFIG, gb_tiling_config);
1385 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1386 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1387 WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
1388 WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
1390 WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));
1391 WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));
1392 WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));
1395 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1396 WREG32(CGTS_TCC_DISABLE, 0);
1397 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1398 WREG32(CGTS_USER_TCC_DISABLE, 0);
1402 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
1403 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1406 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1409 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1412 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
1416 WREG32(SX_DEBUG_1, sx_debug_1);
1421 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1424 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
1430 WREG32(SMX_SAR_CTL0, 0x00003f3f);
1445 WREG32(DB_DEBUG3, db_debug3);
1450 WREG32(DB_DEBUG4, db_debug4);
1453 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
1457 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
1461 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1463 WREG32(VGT_NUM_INSTANCES, 1);
1465 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1467 WREG32(CP_PERFMON_CNTL, 0);
1483 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1504 WREG32(SQ_CONFIG, sq_config);
1506 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
1510 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
1520 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1522 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
1525 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
1533 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1534 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1535 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1536 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1537 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1538 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1539 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1540 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1542 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1546 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
1549 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
1571 WREG32(VGT_ES_PER_GS, 128);
1572 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
1573 WREG32(VGT_GS_PER_VS, 2);
1576 WREG32(VGT_GS_VERTEX_REUSE, 16);
1577 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1578 WREG32(VGT_STRMOUT_EN, 0);
1579 WREG32(SX_MISC, 0);
1580 WREG32(PA_SC_MODE_CNTL, 0);
1581 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
1582 WREG32(PA_SC_AA_CONFIG, 0);
1583 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
1584 WREG32(PA_SC_LINE_STIPPLE, 0);
1585 WREG32(SPI_INPUT_Z, 0);
1586 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1587 WREG32(CB_COLOR7_FRAG, 0);
1590 WREG32(CB_COLOR0_BASE, 0);
1591 WREG32(CB_COLOR1_BASE, 0);
1592 WREG32(CB_COLOR2_BASE, 0);
1593 WREG32(CB_COLOR3_BASE, 0);
1594 WREG32(CB_COLOR4_BASE, 0);
1595 WREG32(CB_COLOR5_BASE, 0);
1596 WREG32(CB_COLOR6_BASE, 0);
1597 WREG32(CB_COLOR7_BASE, 0);
1599 WREG32(TCP_CNTL, 0);
1602 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1604 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1606 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1608 WREG32(VC_ENHANCE, 0);
2076 WREG32(0x541c, tmp | 0x8);
2077 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
2082 WREG32(MM_CFGREGS_CNTL, 0);
Indexes created Mon Oct 20 16:09:52 GMT 2025