Lines Matching refs:cbs
124 static int vmw_binding_emit_dirty(struct vmw_ctx_binding_state *cbs);
240 * @cbs: The context binding state tracker.
249 vmw_cbs_context(const struct vmw_ctx_binding_state *cbs)
251 if (list_empty(&cbs->list))
254 return list_first_entry(&cbs->list, struct vmw_ctx_bindinfo,
261 * @cbs: Pointer to a struct vmw_ctx_binding state which holds the slot.
267 vmw_binding_loc(struct vmw_ctx_binding_state *cbs,
273 return (struct vmw_ctx_bindinfo *)((u8 *) cbs + offset);
296 * @cbs: Pointer to the context binding state tracker.
300 * state structure @cbs.
302 void vmw_binding_add(struct vmw_ctx_binding_state *cbs,
307 vmw_binding_loc(cbs, bi->bt, shader_slot, slot);
315 list_add(&loc->ctx_list, &cbs->list);
322 * @cbs: Pointer to the persistent context binding state tracker.
326 static void vmw_binding_transfer(struct vmw_ctx_binding_state *cbs,
332 ((unsigned long) cbs + offset);
342 list_add_tail(&loc->ctx_list, &cbs->list);
351 * @cbs: Pointer to the context binding state tracker.
356 void vmw_binding_state_kill(struct vmw_ctx_binding_state *cbs)
360 vmw_binding_state_scrub(cbs);
361 list_for_each_entry_safe(entry, next, &cbs->list, ctx_list)
369 * @cbs: Pointer to the context binding state tracker.
374 void vmw_binding_state_scrub(struct vmw_ctx_binding_state *cbs)
378 list_for_each_entry(entry, &cbs->list, ctx_list) {
386 (void) vmw_binding_emit_dirty(cbs);
429 struct vmw_ctx_binding_state *cbs =
432 (void) vmw_binding_emit_dirty(cbs);
468 int vmw_binding_rebind_all(struct vmw_ctx_binding_state *cbs)
473 list_for_each_entry(entry, &cbs->list, ctx_list) {
488 return vmw_binding_emit_dirty(cbs);
664 * @cbs: Pointer to the context's struct vmw_ctx_binding_state
665 * @bi: Pointer to where the binding info array is stored in @cbs
670 * On output, @cbs->bind_cmd_count contains the number of bindings to be
671 * emitted, @cbs->bind_first_slot is set to zero, and @cbs->bind_cmd_buffer
674 static void vmw_collect_view_ids(struct vmw_ctx_binding_state *cbs,
682 cbs->bind_cmd_count = 0;
683 cbs->bind_first_slot = 0;
689 cbs->bind_cmd_buffer[cbs->bind_cmd_count++] =
698 * @cbs: Pointer to the context's struct vmw_ctx_binding_state
699 * @bi: Pointer to where the binding info array is stored in @cbs
705 * On output, @cbs->bind_cmd_count contains the number of bindings to be
706 * emitted, @cbs->bind_first_slot indicates the index of the first emitted
707 * binding, and @cbs->bind_cmd_buffer contains the command data.
709 static void vmw_collect_dirty_view_ids(struct vmw_ctx_binding_state *cbs,
718 cbs->bind_cmd_count = 0;
721 cbs->bind_first_slot = i;
725 cbs->bind_cmd_buffer[cbs->bind_cmd_count++] =
740 * @cbs: Pointer to the context's struct vmw_ctx_binding_state
742 static int vmw_emit_set_sr(struct vmw_ctx_binding_state *cbs,
746 &cbs->per_shader[shader_slot].shader_res[0].bi;
752 const struct vmw_resource *ctx = vmw_cbs_context(cbs);
754 vmw_collect_dirty_view_ids(cbs, loc,
755 cbs->per_shader[shader_slot].dirty_sr,
757 if (cbs->bind_cmd_count == 0)
760 view_id_size = cbs->bind_cmd_count*sizeof(uint32);
769 cmd->body.startView = cbs->bind_first_slot;
771 memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
774 bitmap_clear(cbs->per_shader[shader_slot].dirty_sr,
775 cbs->bind_first_slot, cbs->bind_cmd_count);
783 * @cbs: Pointer to the context's struct vmw_ctx_binding_state
785 static int vmw_emit_set_rt(struct vmw_ctx_binding_state *cbs)
787 const struct vmw_ctx_bindinfo *loc = &cbs->render_targets[0].bi;
793 const struct vmw_resource *ctx = vmw_cbs_context(cbs);
795 vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS);
796 view_id_size = cbs->bind_cmd_count*sizeof(uint32);
805 if (cbs->ds_view.bi.ctx && !cbs->ds_view.bi.scrubbed)
806 cmd->body.depthStencilViewId = cbs->ds_view.bi.res->id;
810 memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
822 * @cbs: Pointer to the context's struct vmw_ctx_binding_state
823 * @bi: Pointer to where the binding info array is stored in @cbs
828 * On output, @cbs->bind_cmd_count contains the number of bindings to be
829 * emitted, @cbs->bind_first_slot is set to zero, and @cbs->bind_cmd_buffer
832 static void vmw_collect_so_targets(struct vmw_ctx_binding_state *cbs,
839 SVGA3dSoTarget *so_buffer = (SVGA3dSoTarget *) cbs->bind_cmd_buffer;
841 cbs->bind_cmd_count = 0;
842 cbs->bind_first_slot = 0;
845 ++cbs->bind_cmd_count) {
864 * @cbs: Pointer to the context's struct vmw_ctx_binding_state
866 static int vmw_emit_set_so(struct vmw_ctx_binding_state *cbs)
868 const struct vmw_ctx_bindinfo *loc = &cbs->so_targets[0].bi;
874 const struct vmw_resource *ctx = vmw_cbs_context(cbs);
876 vmw_collect_so_targets(cbs, loc, SVGA3D_DX_MAX_SOTARGETS);
877 if (cbs->bind_cmd_count == 0)
880 so_target_size = cbs->bind_cmd_count*sizeof(SVGA3dSoTarget);
888 memcpy(&cmd[1], cbs->bind_cmd_buffer, so_target_size);
899 * @cbs: Pointer to the context's struct vmw_ctx_binding_state
902 static int vmw_binding_emit_dirty_ps(struct vmw_ctx_binding_state *cbs)
904 struct vmw_dx_shader_bindings *sb = &cbs->per_shader[0];
912 ret = vmw_emit_set_sr(cbs, i);
926 * @cbs: Pointer to the context's struct vmw_ctx_binding_state
927 * @bi: Pointer to where the binding info array is stored in @cbs
933 * On output, @cbs->bind_cmd_count contains the number of bindings to be
934 * emitted, @cbs->bind_first_slot indicates the index of the first emitted
935 * binding, and @cbs->bind_cmd_buffer contains the command data.
937 static void vmw_collect_dirty_vbs(struct vmw_ctx_binding_state *cbs,
945 SVGA3dVertexBuffer *vbs = (SVGA3dVertexBuffer *) &cbs->bind_cmd_buffer;
947 cbs->bind_cmd_count = 0;
950 cbs->bind_first_slot = i;
963 cbs->bind_cmd_count++;
975 * @cbs: Pointer to the context's struct vmw_ctx_binding_state
978 static int vmw_emit_set_vb(struct vmw_ctx_binding_state *cbs)
981 &cbs->vertex_buffers[0].bi;
987 const struct vmw_resource *ctx = vmw_cbs_context(cbs);
989 vmw_collect_dirty_vbs(cbs, loc, cbs->dirty_vb,
991 if (cbs->bind_cmd_count == 0)
994 set_vb_size = cbs->bind_cmd_count*sizeof(SVGA3dVertexBuffer);
1002 cmd->body.startBuffer = cbs->bind_first_slot;
1004 memcpy(&cmd[1], cbs->bind_cmd_buffer, set_vb_size);
1007 bitmap_clear(cbs->dirty_vb,
1008 cbs->bind_first_slot, cbs->bind_cmd_count);
1016 * @cbs: Pointer to the context's struct vmw_ctx_binding_state
1023 static int vmw_binding_emit_dirty(struct vmw_ctx_binding_state *cbs)
1028 while ((hit = find_next_bit(&cbs->dirty, VMW_BINDING_NUM_BITS, hit))
1033 ret = vmw_emit_set_rt(cbs);
1036 ret = vmw_binding_emit_dirty_ps(cbs);
1039 ret = vmw_emit_set_so(cbs);
1042 ret = vmw_emit_set_vb(cbs);
1050 __clear_bit(hit, &cbs->dirty);
1068 struct vmw_ctx_binding_state *cbs =
1071 __set_bit(biv->slot, cbs->per_shader[biv->shader_slot].dirty_sr);
1073 &cbs->per_shader[biv->shader_slot].dirty);
1074 __set_bit(VMW_BINDING_PS_BIT, &cbs->dirty);
1088 struct vmw_ctx_binding_state *cbs =
1091 __set_bit(VMW_BINDING_RT_BIT, &cbs->dirty);
1105 struct vmw_ctx_binding_state *cbs =
1108 __set_bit(VMW_BINDING_SO_BIT, &cbs->dirty);
1124 struct vmw_ctx_binding_state *cbs =
1127 __set_bit(bivb->slot, cbs->dirty_vb);
1128 __set_bit(VMW_BINDING_VB_BIT, &cbs->dirty);
1181 struct vmw_ctx_binding_state *cbs;
1188 ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), sizeof(*cbs),
1193 cbs = vzalloc(sizeof(*cbs));
1194 if (!cbs) {
1195 ttm_mem_global_free(vmw_mem_glob(dev_priv), sizeof(*cbs));
1199 cbs->dev_priv = dev_priv;
1200 INIT_LIST_HEAD(&cbs->list);
1202 return cbs;
1209 * @cbs: Pointer to the struct vmw_ctx_binding_state to be freed.
1211 void vmw_binding_state_free(struct vmw_ctx_binding_state *cbs)
1213 struct vmw_private *dev_priv = cbs->dev_priv;
1215 vfree(cbs);
1216 ttm_mem_global_free(vmw_mem_glob(dev_priv), sizeof(*cbs));
1223 * @cbs: Pointer to the struct vmw_ctx_binding_state
1228 struct list_head *vmw_binding_state_list(struct vmw_ctx_binding_state *cbs)
1230 return &cbs->list;
1236 * @cbs: Pointer to the struct vmw_ctx_binding_state to be cleared
1238 * Drops all bindings registered in @cbs. No device binding actions are
1241 void vmw_binding_state_reset(struct vmw_ctx_binding_state *cbs)
1245 list_for_each_entry_safe(entry, next, &cbs->list, ctx_list)
Indexes created Thu Oct 02 07:10:07 GMT 2025