Lines Matching refs:info
40 #define INTEL_VGA_DEVICE(id, info) { \
44 (unsigned long) info }
46 #define INTEL_QUANTA_VGA_DEVICE(info) { \
50 (unsigned long) info }
52 #define INTEL_I810_IDS(info) \
53 INTEL_VGA_DEVICE(0x7121, info), /* I810 */ \
54 INTEL_VGA_DEVICE(0x7123, info), /* I810_DC100 */ \
55 INTEL_VGA_DEVICE(0x7125, info) /* I810_E */
57 #define INTEL_I815_IDS(info) \
58 INTEL_VGA_DEVICE(0x1132, info) /* I815*/
60 #define INTEL_I830_IDS(info) \
61 INTEL_VGA_DEVICE(0x3577, info)
63 #define INTEL_I845G_IDS(info) \
64 INTEL_VGA_DEVICE(0x2562, info)
66 #define INTEL_I85X_IDS(info) \
67 INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
68 INTEL_VGA_DEVICE(0x358e, info)
70 #define INTEL_I865G_IDS(info) \
71 INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
73 #define INTEL_I915G_IDS(info) \
74 INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
75 INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
77 #define INTEL_I915GM_IDS(info) \
78 INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
80 #define INTEL_I945G_IDS(info) \
81 INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
83 #define INTEL_I945GM_IDS(info) \
84 INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
85 INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
87 #define INTEL_I965G_IDS(info) \
88 INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
89 INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
90 INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
91 INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
93 #define INTEL_G33_IDS(info) \
94 INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
95 INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
96 INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
98 #define INTEL_I965GM_IDS(info) \
99 INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
100 INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
102 #define INTEL_GM45_IDS(info) \
103 INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
105 #define INTEL_G45_IDS(info) \
106 INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
107 INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
108 INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
109 INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
110 INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
111 INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
113 #define INTEL_PINEVIEW_G_IDS(info) \
114 INTEL_VGA_DEVICE(0xa001, info)
116 #define INTEL_PINEVIEW_M_IDS(info) \
117 INTEL_VGA_DEVICE(0xa011, info)
119 #define INTEL_IRONLAKE_D_IDS(info) \
120 INTEL_VGA_DEVICE(0x0042, info)
122 #define INTEL_IRONLAKE_M_IDS(info) \
123 INTEL_VGA_DEVICE(0x0046, info)
125 #define INTEL_SNB_D_GT1_IDS(info) \
126 INTEL_VGA_DEVICE(0x0102, info), \
127 INTEL_VGA_DEVICE(0x010A, info)
129 #define INTEL_SNB_D_GT2_IDS(info) \
130 INTEL_VGA_DEVICE(0x0112, info), \
131 INTEL_VGA_DEVICE(0x0122, info)
133 #define INTEL_SNB_D_IDS(info) \
134 INTEL_SNB_D_GT1_IDS(info), \
135 INTEL_SNB_D_GT2_IDS(info)
137 #define INTEL_SNB_M_GT1_IDS(info) \
138 INTEL_VGA_DEVICE(0x0106, info)
140 #define INTEL_SNB_M_GT2_IDS(info) \
141 INTEL_VGA_DEVICE(0x0116, info), \
142 INTEL_VGA_DEVICE(0x0126, info)
144 #define INTEL_SNB_M_IDS(info) \
145 INTEL_SNB_M_GT1_IDS(info), \
146 INTEL_SNB_M_GT2_IDS(info)
148 #define INTEL_IVB_M_GT1_IDS(info) \
149 INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */
151 #define INTEL_IVB_M_GT2_IDS(info) \
152 INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
154 #define INTEL_IVB_M_IDS(info) \
155 INTEL_IVB_M_GT1_IDS(info), \
156 INTEL_IVB_M_GT2_IDS(info)
158 #define INTEL_IVB_D_GT1_IDS(info) \
159 INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
160 INTEL_VGA_DEVICE(0x015a, info) /* GT1 server */
162 #define INTEL_IVB_D_GT2_IDS(info) \
163 INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
164 INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
166 #define INTEL_IVB_D_IDS(info) \
167 INTEL_IVB_D_GT1_IDS(info), \
168 INTEL_IVB_D_GT2_IDS(info)
170 #define INTEL_IVB_Q_IDS(info) \
171 INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
173 #define INTEL_HSW_ULT_GT1_IDS(info) \
174 INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
175 INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
176 INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
177 INTEL_VGA_DEVICE(0x0A06, info) /* ULT GT1 mobile */
179 #define INTEL_HSW_ULX_GT1_IDS(info) \
180 INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */
182 #define INTEL_HSW_GT1_IDS(info) \
183 INTEL_HSW_ULT_GT1_IDS(info), \
184 INTEL_HSW_ULX_GT1_IDS(info), \
185 INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
186 INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
187 INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
188 INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
189 INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
190 INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
191 INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
192 INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
193 INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
194 INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
195 INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
196 INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
197 INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
198 INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
199 INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */
201 #define INTEL_HSW_ULT_GT2_IDS(info) \
202 INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
203 INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
204 INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
205 INTEL_VGA_DEVICE(0x0A16, info) /* ULT GT2 mobile */
207 #define INTEL_HSW_ULX_GT2_IDS(info) \
208 INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \
210 #define INTEL_HSW_GT2_IDS(info) \
211 INTEL_HSW_ULT_GT2_IDS(info), \
212 INTEL_HSW_ULX_GT2_IDS(info), \
213 INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
214 INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
215 INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
216 INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
217 INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
218 INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
219 INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
220 INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
221 INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
222 INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
223 INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
224 INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
225 INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
226 INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
227 INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
228 INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */
230 #define INTEL_HSW_ULT_GT3_IDS(info) \
231 INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
232 INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
233 INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
234 INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
235 INTEL_VGA_DEVICE(0x0A2E, info) /* ULT GT3 reserved */
237 #define INTEL_HSW_GT3_IDS(info) \
238 INTEL_HSW_ULT_GT3_IDS(info), \
239 INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
240 INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
241 INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
242 INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
243 INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
244 INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
245 INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
246 INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
247 INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
248 INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
249 INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
250 INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
251 INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
252 INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
254 #define INTEL_HSW_IDS(info) \
255 INTEL_HSW_GT1_IDS(info), \
256 INTEL_HSW_GT2_IDS(info), \
257 INTEL_HSW_GT3_IDS(info)
259 #define INTEL_VLV_IDS(info) \
260 INTEL_VGA_DEVICE(0x0f30, info), \
261 INTEL_VGA_DEVICE(0x0f31, info), \
262 INTEL_VGA_DEVICE(0x0f32, info), \
263 INTEL_VGA_DEVICE(0x0f33, info), \
264 INTEL_VGA_DEVICE(0x0157, info), \
265 INTEL_VGA_DEVICE(0x0155, info)
267 #define INTEL_BDW_ULT_GT1_IDS(info) \
268 INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
269 INTEL_VGA_DEVICE(0x160B, info) /* GT1 Iris */
271 #define INTEL_BDW_ULX_GT1_IDS(info) \
272 INTEL_VGA_DEVICE(0x160E, info) /* GT1 ULX */
274 #define INTEL_BDW_GT1_IDS(info) \
275 INTEL_BDW_ULT_GT1_IDS(info), \
276 INTEL_BDW_ULX_GT1_IDS(info), \
277 INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
278 INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
279 INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
281 #define INTEL_BDW_ULT_GT2_IDS(info) \
282 INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
283 INTEL_VGA_DEVICE(0x161B, info) /* GT2 ULT */
285 #define INTEL_BDW_ULX_GT2_IDS(info) \
286 INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
288 #define INTEL_BDW_GT2_IDS(info) \
289 INTEL_BDW_ULT_GT2_IDS(info), \
290 INTEL_BDW_ULX_GT2_IDS(info), \
291 INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
292 INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
293 INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
295 #define INTEL_BDW_ULT_GT3_IDS(info) \
296 INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
297 INTEL_VGA_DEVICE(0x162B, info) /* Iris */ \
299 #define INTEL_BDW_ULX_GT3_IDS(info) \
300 INTEL_VGA_DEVICE(0x162E, info) /* ULX */
302 #define INTEL_BDW_GT3_IDS(info) \
303 INTEL_BDW_ULT_GT3_IDS(info), \
304 INTEL_BDW_ULX_GT3_IDS(info), \
305 INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
306 INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
307 INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
309 #define INTEL_BDW_ULT_RSVD_IDS(info) \
310 INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
311 INTEL_VGA_DEVICE(0x163B, info) /* Iris */
313 #define INTEL_BDW_ULX_RSVD_IDS(info) \
314 INTEL_VGA_DEVICE(0x163E, info) /* ULX */
316 #define INTEL_BDW_RSVD_IDS(info) \
317 INTEL_BDW_ULT_RSVD_IDS(info), \
318 INTEL_BDW_ULX_RSVD_IDS(info), \
319 INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
320 INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
321 INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
323 #define INTEL_BDW_IDS(info) \
324 INTEL_BDW_GT1_IDS(info), \
325 INTEL_BDW_GT2_IDS(info), \
326 INTEL_BDW_GT3_IDS(info), \
327 INTEL_BDW_RSVD_IDS(info)
329 #define INTEL_CHV_IDS(info) \
330 INTEL_VGA_DEVICE(0x22b0, info), \
331 INTEL_VGA_DEVICE(0x22b1, info), \
332 INTEL_VGA_DEVICE(0x22b2, info), \
333 INTEL_VGA_DEVICE(0x22b3, info)
335 #define INTEL_SKL_ULT_GT1_IDS(info) \
336 INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */
338 #define INTEL_SKL_ULX_GT1_IDS(info) \
339 INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */
341 #define INTEL_SKL_GT1_IDS(info) \
342 INTEL_SKL_ULT_GT1_IDS(info), \
343 INTEL_SKL_ULX_GT1_IDS(info), \
344 INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
345 INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
346 INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
348 #define INTEL_SKL_ULT_GT2_IDS(info) \
349 INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
350 INTEL_VGA_DEVICE(0x1921, info) /* ULT GT2F */
352 #define INTEL_SKL_ULX_GT2_IDS(info) \
353 INTEL_VGA_DEVICE(0x191E, info) /* ULX GT2 */
355 #define INTEL_SKL_GT2_IDS(info) \
356 INTEL_SKL_ULT_GT2_IDS(info), \
357 INTEL_SKL_ULX_GT2_IDS(info), \
358 INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
359 INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
360 INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
361 INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
363 #define INTEL_SKL_ULT_GT3_IDS(info) \
364 INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */
366 #define INTEL_SKL_GT3_IDS(info) \
367 INTEL_SKL_ULT_GT3_IDS(info), \
368 INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
369 INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
370 INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
371 INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */
373 #define INTEL_SKL_GT4_IDS(info) \
374 INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
375 INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
376 INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
377 INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \
378 INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */
380 #define INTEL_SKL_IDS(info) \
381 INTEL_SKL_GT1_IDS(info), \
382 INTEL_SKL_GT2_IDS(info), \
383 INTEL_SKL_GT3_IDS(info), \
384 INTEL_SKL_GT4_IDS(info)
386 #define INTEL_BXT_IDS(info) \
387 INTEL_VGA_DEVICE(0x0A84, info), \
388 INTEL_VGA_DEVICE(0x1A84, info), \
389 INTEL_VGA_DEVICE(0x1A85, info), \
390 INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
391 INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
393 #define INTEL_GLK_IDS(info) \
394 INTEL_VGA_DEVICE(0x3184, info), \
395 INTEL_VGA_DEVICE(0x3185, info)
397 #define INTEL_KBL_ULT_GT1_IDS(info) \
398 INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
399 INTEL_VGA_DEVICE(0x5913, info) /* ULT GT1.5 */
401 #define INTEL_KBL_ULX_GT1_IDS(info) \
402 INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
403 INTEL_VGA_DEVICE(0x5915, info) /* ULX GT1.5 */
405 #define INTEL_KBL_GT1_IDS(info) \
406 INTEL_KBL_ULT_GT1_IDS(info), \
407 INTEL_KBL_ULX_GT1_IDS(info), \
408 INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
409 INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
410 INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
411 INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
413 #define INTEL_KBL_ULT_GT2_IDS(info) \
414 INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
415 INTEL_VGA_DEVICE(0x5921, info) /* ULT GT2F */
417 #define INTEL_KBL_ULX_GT2_IDS(info) \
418 INTEL_VGA_DEVICE(0x591E, info) /* ULX GT2 */
420 #define INTEL_KBL_GT2_IDS(info) \
421 INTEL_KBL_ULT_GT2_IDS(info), \
422 INTEL_KBL_ULX_GT2_IDS(info), \
423 INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
424 INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
425 INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
426 INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
427 INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
429 #define INTEL_KBL_ULT_GT3_IDS(info) \
430 INTEL_VGA_DEVICE(0x5926, info) /* ULT GT3 */
432 #define INTEL_KBL_GT3_IDS(info) \
433 INTEL_KBL_ULT_GT3_IDS(info), \
434 INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
435 INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
437 #define INTEL_KBL_GT4_IDS(info) \
438 INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
441 #define INTEL_AML_KBL_GT2_IDS(info) \
442 INTEL_VGA_DEVICE(0x591C, info), /* ULX GT2 */ \
443 INTEL_VGA_DEVICE(0x87C0, info) /* ULX GT2 */
446 #define INTEL_AML_CFL_GT2_IDS(info) \
447 INTEL_VGA_DEVICE(0x87CA, info)
450 #define INTEL_CML_GT1_IDS(info) \
451 INTEL_VGA_DEVICE(0x9BA5, info), \
452 INTEL_VGA_DEVICE(0x9BA8, info), \
453 INTEL_VGA_DEVICE(0x9BA4, info), \
454 INTEL_VGA_DEVICE(0x9BA2, info)
456 #define INTEL_CML_U_GT1_IDS(info) \
457 INTEL_VGA_DEVICE(0x9B21, info), \
458 INTEL_VGA_DEVICE(0x9BAA, info), \
459 INTEL_VGA_DEVICE(0x9BAC, info)
462 #define INTEL_CML_GT2_IDS(info) \
463 INTEL_VGA_DEVICE(0x9BC5, info), \
464 INTEL_VGA_DEVICE(0x9BC8, info), \
465 INTEL_VGA_DEVICE(0x9BC4, info), \
466 INTEL_VGA_DEVICE(0x9BC2, info), \
467 INTEL_VGA_DEVICE(0x9BC6, info), \
468 INTEL_VGA_DEVICE(0x9BE6, info), \
469 INTEL_VGA_DEVICE(0x9BF6, info)
471 #define INTEL_CML_U_GT2_IDS(info) \
472 INTEL_VGA_DEVICE(0x9B41, info), \
473 INTEL_VGA_DEVICE(0x9BCA, info), \
474 INTEL_VGA_DEVICE(0x9BCC, info)
476 #define INTEL_KBL_IDS(info) \
477 INTEL_KBL_GT1_IDS(info), \
478 INTEL_KBL_GT2_IDS(info), \
479 INTEL_KBL_GT3_IDS(info), \
480 INTEL_KBL_GT4_IDS(info), \
481 INTEL_AML_KBL_GT2_IDS(info)
484 #define INTEL_CFL_S_GT1_IDS(info) \
485 info), /* SRV GT1 */ \
486 INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
487 INTEL_VGA_DEVICE(0x3E99, info) /* SRV GT1 */
489 #define INTEL_CFL_S_GT2_IDS(info) \
490 INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
491 INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
492 INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \
493 INTEL_VGA_DEVICE(0x3E98, info), /* SRV GT2 */ \
494 INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
497 #define INTEL_CFL_H_GT1_IDS(info) \
498 INTEL_VGA_DEVICE(0x3E9C, info)
500 #define INTEL_CFL_H_GT2_IDS(info) \
501 INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
502 INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
505 #define INTEL_CFL_U_GT2_IDS(info) \
506 INTEL_VGA_DEVICE(0x3EA9, info)
509 #define INTEL_CFL_U_GT3_IDS(info) \
510 INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \
511 INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
512 INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
513 INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */
516 #define INTEL_WHL_U_GT1_IDS(info) \
517 INTEL_VGA_DEVICE(0x3EA1, info), \
518 INTEL_VGA_DEVICE(0x3EA4, info)
521 #define INTEL_WHL_U_GT2_IDS(info) \
522 INTEL_VGA_DEVICE(0x3EA0, info), \
523 INTEL_VGA_DEVICE(0x3EA3, info)
526 #define INTEL_WHL_U_GT3_IDS(info) \
527 INTEL_VGA_DEVICE(0x3EA2, info)
529 #define INTEL_CFL_IDS(info) \
530 INTEL_CFL_S_GT1_IDS(info), \
531 INTEL_CFL_S_GT2_IDS(info), \
532 INTEL_CFL_H_GT1_IDS(info), \
533 INTEL_CFL_H_GT2_IDS(info), \
534 INTEL_CFL_U_GT2_IDS(info), \
535 INTEL_CFL_U_GT3_IDS(info), \
536 INTEL_WHL_U_GT1_IDS(info), \
537 INTEL_WHL_U_GT2_IDS(info), \
538 INTEL_WHL_U_GT3_IDS(info), \
539 INTEL_AML_CFL_GT2_IDS(info), \
540 INTEL_CML_GT1_IDS(info), \
541 INTEL_CML_GT2_IDS(info), \
542 INTEL_CML_U_GT1_IDS(info), \
543 INTEL_CML_U_GT2_IDS(info)
546 #define INTEL_CNL_PORT_F_IDS(info) \
547 INTEL_VGA_DEVICE(0x5A54, info), \
548 INTEL_VGA_DEVICE(0x5A5C, info), \
549 INTEL_VGA_DEVICE(0x5A44, info), \
550 INTEL_VGA_DEVICE(0x5A4C, info)
552 #define INTEL_CNL_IDS(info) \
553 INTEL_CNL_PORT_F_IDS(info), \
554 INTEL_VGA_DEVICE(0x5A51, info), \
555 INTEL_VGA_DEVICE(0x5A59, info), \
556 INTEL_VGA_DEVICE(0x5A41, info), \
557 INTEL_VGA_DEVICE(0x5A49, info), \
558 INTEL_VGA_DEVICE(0x5A52, info), \
559 INTEL_VGA_DEVICE(0x5A5A, info), \
560 INTEL_VGA_DEVICE(0x5A42, info), \
561 INTEL_VGA_DEVICE(0x5A4A, info), \
562 INTEL_VGA_DEVICE(0x5A50, info), \
563 INTEL_VGA_DEVICE(0x5A40, info)
566 #define INTEL_ICL_PORT_F_IDS(info) \
567 INTEL_VGA_DEVICE(0x8A50, info), \
568 INTEL_VGA_DEVICE(0x8A5C, info), \
569 INTEL_VGA_DEVICE(0x8A59, info), \
570 INTEL_VGA_DEVICE(0x8A58, info), \
571 INTEL_VGA_DEVICE(0x8A52, info), \
572 INTEL_VGA_DEVICE(0x8A5A, info), \
573 INTEL_VGA_DEVICE(0x8A5B, info), \
574 INTEL_VGA_DEVICE(0x8A57, info), \
575 INTEL_VGA_DEVICE(0x8A56, info), \
576 INTEL_VGA_DEVICE(0x8A71, info), \
577 INTEL_VGA_DEVICE(0x8A70, info), \
578 INTEL_VGA_DEVICE(0x8A53, info), \
579 INTEL_VGA_DEVICE(0x8A54, info)
581 #define INTEL_ICL_11_IDS(info) \
582 INTEL_ICL_PORT_F_IDS(info), \
583 INTEL_VGA_DEVICE(0x8A51, info), \
584 INTEL_VGA_DEVICE(0x8A5D, info)
587 #define INTEL_EHL_IDS(info) \
588 INTEL_VGA_DEVICE(0x4500, info), \
589 INTEL_VGA_DEVICE(0x4571, info), \
590 INTEL_VGA_DEVICE(0x4551, info), \
591 INTEL_VGA_DEVICE(0x4541, info), \
592 INTEL_VGA_DEVICE(0x4E71, info), \
593 INTEL_VGA_DEVICE(0x4E61, info), \
594 INTEL_VGA_DEVICE(0x4E51, info)
597 #define INTEL_TGL_12_IDS(info) \
598 INTEL_VGA_DEVICE(0x9A49, info), \
599 INTEL_VGA_DEVICE(0x9A40, info), \
600 INTEL_VGA_DEVICE(0x9A59, info), \
601 INTEL_VGA_DEVICE(0x9A60, info), \
602 INTEL_VGA_DEVICE(0x9A68, info), \
603 INTEL_VGA_DEVICE(0x9A70, info), \
604 INTEL_VGA_DEVICE(0x9A78, info)
Indexes created Sat Oct 25 10:09:55 GMT 2025