Lines Matching defs:hsotg
71 * @hsotg: Programming view of DWC_otg controller
80 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
83 int num_channels = hsotg->core_params->host_channels;
94 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num));
95 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chan->hc_num));
96 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chan->hc_num));
97 hc_dma = DWC2_READ_4(hsotg, HCDMA(chan->hc_num));
99 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
100 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
102 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
104 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
106 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
107 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
108 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
109 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
110 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
111 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
112 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
114 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
115 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
116 dev_dbg(hsotg->dev, " NP inactive sched:\n");
117 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
119 dev_dbg(hsotg->dev, " %p\n", qh);
120 dev_dbg(hsotg->dev, " NP waiting sched:\n");
121 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting,
123 dev_dbg(hsotg->dev, " %p\n", qh);
124 dev_dbg(hsotg->dev, " NP active sched:\n");
125 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
127 dev_dbg(hsotg->dev, " %p\n", qh);
128 dev_dbg(hsotg->dev, " Channels:\n");
130 struct dwc2_host_chan *ch = hsotg->hc_ptr_array[i];
132 dev_dbg(hsotg->dev, " %2d: %p\n", i, ch);
143 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
152 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
153 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
158 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
169 spin_lock_irqsave(&hsotg->lock, flags);
172 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
175 dwc2_hcd_qh_unlink(hsotg, qh);
180 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
182 spin_unlock_irqrestore(&hsotg->lock, flags);
183 dwc2_hcd_qh_free(hsotg, qh);
184 spin_lock_irqsave(&hsotg->lock, flags);
187 spin_unlock_irqrestore(&hsotg->lock, flags);
198 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
200 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
201 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting);
202 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
203 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
204 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
205 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
206 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
212 * @hsotg: Pointer to struct dwc2_hsotg
214 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
218 if (hsotg->op_state == OTG_STATE_B_HOST) {
224 hprt0 = dwc2_read_hprt0(hsotg);
226 DWC2_WRITE_4(hsotg, HPRT0, hprt0);
229 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
234 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
236 int num_channels = hsotg->core_params->host_channels;
241 if (hsotg->core_params->dma_enable <= 0) {
244 channel = hsotg->hc_ptr_array[i];
247 hcchar = DWC2_READ_4(hsotg, HCCHAR(i));
251 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar);
257 channel = hsotg->hc_ptr_array[i];
260 hcchar = DWC2_READ_4(hsotg, HCCHAR(i));
264 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar);
267 dwc2_hc_cleanup(hsotg, channel);
268 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
277 if (hsotg->core_params->uframe_sched > 0) {
278 hsotg->available_host_channels =
279 hsotg->core_params->host_channels;
281 hsotg->non_periodic_channels = 0;
282 hsotg->periodic_channels = 0;
289 * @hsotg: Pointer to struct dwc2_hsotg
293 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
295 if (hsotg->lx_state != DWC2_L0)
296 usb_hcd_resume_root_hub(hsotg->priv);
298 hsotg->flags.b.port_connect_status_change = 1;
299 hsotg->flags.b.port_connect_status = 1;
305 * @hsotg: Pointer to struct dwc2_hsotg
310 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
316 hsotg->flags.b.port_connect_status_change = 1;
317 hsotg->flags.b.port_connect_status = 0;
324 intr = DWC2_READ_4(hsotg, GINTMSK);
326 DWC2_WRITE_4(hsotg, GINTMSK, intr);
328 DWC2_WRITE_4(hsotg, GINTSTS, intr);
335 if (dwc2_is_device_mode(hsotg)) {
336 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
337 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
338 DWC2_WRITE_4(hsotg, HPRT0, 0);
341 dwc2_disable_host_interrupts(hsotg);
345 dwc2_kill_all_urbs(hsotg);
347 if (dwc2_is_host_mode(hsotg))
349 dwc2_hcd_cleanup_channels(hsotg);
351 dwc2_host_disconnect(hsotg);
353 dwc2_root_intr(hsotg->hsotg_sc);
368 hprt0 = DWC2_READ_4(hsotg, HPRT0);
370 dwc2_hcd_connect(hsotg);
377 * @hsotg: Pointer to struct dwc2_hsotg
379 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
381 if (hsotg->bus_suspended) {
382 hsotg->flags.b.port_suspend_change = 1;
383 usb_hcd_resume_root_hub(hsotg->priv);
386 if (hsotg->lx_state == DWC2_L1)
387 hsotg->flags.b.port_l1_change = 1;
389 dwc2_root_intr(hsotg->hsotg_sc);
395 * @hsotg: Pointer to struct dwc2_hsotg
399 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
401 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
410 dwc2_disable_host_interrupts(hsotg);
413 dev_dbg(hsotg->dev, "PortPower off\n");
414 DWC2_WRITE_4(hsotg, HPRT0, 0);
418 int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
426 if (!hsotg->flags.b.port_connect_status) {
428 dev_err(hsotg->dev, "Not connected\n");
432 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
436 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
437 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
438 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0);
442 dev_err(hsotg->dev,
454 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
456 dev_err(hsotg->dev,
462 intr_mask = DWC2_READ_4(hsotg, GINTMSK);
474 tr_type = dwc2_hcd_select_transactions(hsotg);
476 dwc2_hcd_queue_transactions(hsotg, tr_type);
484 dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
492 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
498 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
506 dwc2_dump_channel_info(hsotg, qh->channel);
509 if (hsotg->flags.b.port_connect_status)
517 dwc2_hc_halt(hsotg, qh->channel,
525 if (hsotg->core_params->dma_desc_enable <= 0) {
528 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
530 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
533 dwc2_hcd_qh_unlink(hsotg, qh);
536 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
549 dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
555 hsotg
556 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
558 if (hsotg->core_params->uframe_sched > 0) {
559 hsotg->available_host_channels =
560 hsotg->core_params->host_channels;
562 hsotg->non_periodic_channels = 0;
563 hsotg->periodic_channels = 0;
570 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
574 num_channels = hsotg->core_params->host_channels;
576 chan = hsotg->hc_ptr_array[i];
577 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
578 dwc2_hc_cleanup(hsotg, chan);
582 dwc2_core_host_init(hsotg);
585 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
594 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
599 static void *dwc2_hc_init_xfer_data(struct dwc2_hsotg *hsotg,
603 if (hsotg->core_params->dma_enable > 0) {
607 if (hsotg->core_params->dma_desc_enable <= 0 &&
617 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
630 dev_vdbg(hsotg->dev, " Control setup transaction\n");
634 if (hsotg->core_params->dma_enable > 0)
642 dev_vdbg(hsotg->dev, " Control data transaction\n");
644 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb);
652 dev_vdbg(hsotg->dev, " Control status transaction\n");
662 if (hsotg->core_params->dma_enable > 0)
663 chan->xfer_dma = hsotg->status_buf_dma;
665 chan->xfer_buf = hsotg->status_buf;
672 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb);
677 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb);
682 if (hsotg->core_params->dma_desc_enable > 0)
688 if (hsotg->core_params->dma_enable > 0) {
701 if (hsotg->core_params->dma_enable > 0 &&
718 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
728 buf_size = hsotg->core_params->max_transfer_size;
735 err = usb_allocmem(hsotg->hsotg_sc->sc_bus.ub_dmatag,
749 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
758 dev_warn(hsotg->dev, "no URB in dwc2_urb\n");
774 * @hsotg: The HCD state structure
778 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
786 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
789 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
793 if (list_empty(&hsotg->free_hc_list)) {
794 dev_dbg(hsotg->dev, "No free channel to assign\n");
798 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
850 dwc2_hc_init_split(hsotg, chan, qtd, urb);
855 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, urb);
859 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
860 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) {
861 dev_err(hsotg->dev,
868 &hsotg->free_hc_list);
885 if (hsotg->core_params->dma_desc_enable > 0) {
891 dwc2_hc_init(hsotg, chan);
902 * @hsotg: The HCD state structure
907 struct dwc2_hsotg *hsotg)
915 dev_vdbg(hsotg->dev, " Select Transactions\n");
919 qh_ptr = hsotg->periodic_sched_ready.next;
920 while (qh_ptr != &hsotg->periodic_sched_ready) {
921 if (list_empty(&hsotg->free_hc_list))
923 if (hsotg->core_params->uframe_sched > 0) {
924 if (hsotg->available_host_channels <= 1)
926 hsotg->available_host_channels--;
929 if (dwc2_assign_and_init_hc(hsotg, qh))
937 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned);
946 num_channels = hsotg->core_params->host_channels;
947 qh_ptr = hsotg->non_periodic_sched_inactive.next;
948 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
949 if (hsotg->core_params->uframe_sched <= 0 &&
950 hsotg->non_periodic_channels >= num_channels -
951 hsotg->periodic_channels)
953 if (list_empty(&hsotg->free_hc_list))
965 dwc2_full_frame_num(dwc2_hcd_get_frame_number(hsotg))) {
972 if (hsotg->core_params->uframe_sched > 0) {
973 if (hsotg->available_host_channels < 1)
975 hsotg->available_host_channels--;
978 if (dwc2_assign_and_init_hc(hsotg, qh))
987 &hsotg->non_periodic_sched_active);
994 if (hsotg->core_params->uframe_sched <= 0)
995 hsotg->non_periodic_channels++;
1005 * @hsotg: The HCD state structure
1022 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
1028 if (hsotg->core_params->dma_enable > 0) {
1029 if (hsotg->core_params->dma_desc_enable > 0) {
1032 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
1036 dwc2_hc_start_transfer(hsotg, chan);
1042 dwc2_hc_halt(hsotg, chan, chan->halt_status);
1045 dwc2_hc_start_transfer(hsotg, chan);
1050 dwc2_hc_start_transfer(hsotg, chan);
1053 retval = dwc2_hc_continue_transfer(hsotg, chan);
1060 dwc2_hc_start_transfer(hsotg, chan);
1063 retval = dwc2_hc_continue_transfer(hsotg, chan);
1079 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
1092 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
1094 tx_status = DWC2_READ_4(hsotg, HPTXSTS);
1101 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
1103 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
1107 qh_ptr = hsotg->periodic_sched_assigned.next;
1108 while (qh_ptr != &hsotg->periodic_sched_assigned) {
1109 tx_status = DWC2_READ_4(hsotg, HPTXSTS);
1134 if (hsotg->core_params->dma_enable <= 0 &&
1136 hsotg->queuing_high_bandwidth = 1;
1140 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1153 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1161 &hsotg->periodic_sched_queued);
1164 hsotg->queuing_high_bandwidth = 0;
1168 if (hsotg->core_params->dma_enable <= 0) {
1169 tx_status = DWC2_READ_4(hsotg, HPTXSTS);
1175 dev_vdbg(hsotg->dev,
1178 dev_vdbg(hsotg->dev,
1183 if (!list_empty(&hsotg->periodic_sched_assigned) ||
1192 gintmsk = DWC2_READ_4(hsotg, GINTMSK);
1194 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk);
1203 gintmsk = DWC2_READ_4(hsotg, GINTMSK);
1205 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk);
1219 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1232 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1234 tx_status = DWC2_READ_4(hsotg, GNPTXSTS);
1239 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
1241 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
1248 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1249 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1250 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1257 tx_status = DWC2_READ_4(hsotg, GNPTXSTS);
1260 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1265 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1276 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1286 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1287 if (hsotg->non_periodic_qh_ptr ==
1288 &hsotg->non_periodic_sched_active)
1289 hsotg->non_periodic_qh_ptr =
1290 hsotg->non_periodic_qh_ptr->next;
1291 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1293 if (hsotg->core_params->dma_enable <= 0) {
1294 tx_status = DWC2_READ_4(hsotg, GNPTXSTS);
1299 dev_vdbg(hsotg->dev,
1302 dev_vdbg(hsotg->dev,
1314 gintmsk = DWC2_READ_4(hsotg, GINTMSK);
1316 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk);
1325 gintmsk = DWC2_READ_4(hsotg, GINTMSK);
1327 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk);
1337 * @hsotg: The HCD state structure
1343 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1347 dev_vdbg(hsotg->dev, "Queue Transactions\n");
1352 !list_empty(&hsotg->periodic_sched_assigned))
1353 dwc2_process_periodic_channels(hsotg);
1358 if (!list_empty(&hsotg->non_periodic_sched_active)) {
1359 dwc2_process_non_periodic_channels(hsotg);
1365 u32 gintmsk = DWC2_READ_4(hsotg, GINTMSK);
1368 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk);
1375 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1381 dev_dbg(hsotg->dev, "%s()\n", __func__);
1383 gotgctl = DWC2_READ_4(hsotg, GOTGCTL);
1384 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1385 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1391 dev_dbg(hsotg->dev, "connId B\n");
1392 while (!dwc2_is_device_mode(hsotg)) {
1393 dev_info(hsotg->dev,
1395 dwc2_is_host_mode(hsotg) ? "Host" :
1402 dev_err(hsotg->dev,
1404 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
1405 dwc2_core_init(hsotg, false);
1406 dwc2_enable_global_interrupts(hsotg);
1407 spin_lock_irqsave(&hsotg->lock, flags);
1408 dwc2_hsotg_core_init_disconnected(hsotg, false);
1409 spin_unlock_irqrestore(&hsotg->lock, flags);
1410 dwc2_hsotg_core_connect(hsotg);
1413 dev_dbg(hsotg->dev, "connId A\n");
1414 while (!dwc2_is_host_mode(hsotg)) {
1415 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1416 dwc2_is_host_mode(hsotg) ?
1423 dev_err(hsotg->dev,
1425 hsotg->op_state = OTG_STATE_A_HOST;
1428 dwc2_core_init(hsotg, false);
1429 dwc2_enable_global_interrupts(hsotg);
1430 dwc2_hcd_start(hsotg);
1436 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1439 dev_dbg(hsotg->dev, "%s()\n", __func__);
1445 hprt0 = dwc2_read_hprt0(hsotg);
1446 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1448 DWC2_WRITE_4(hsotg, HPRT0, hprt0);
1449 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
1450 DWC2_READ_4(hsotg, HPRT0));
1452 dwc2_hcd_rem_wakeup(hsotg);
1453 hsotg->bus_suspended = 0;
1456 hsotg->lx_state = DWC2_L0;
1460 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1467 dev_dbg(hsotg->dev, "%s()\n", __func__);
1469 spin_lock_irqsave(&hsotg->lock, flags);
1471 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
1472 gotgctl = DWC2_READ_4(hsotg, GOTGCTL);
1474 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl);
1475 hsotg->op_state = OTG_STATE_A_SUSPEND;
1478 hprt0 = dwc2_read_hprt0(hsotg);
1480 DWC2_WRITE_4(hsotg, HPRT0, hprt0);
1482 hsotg->bus_suspended = 1;
1488 if (!hsotg->core_params->hibernation) {
1490 pcgctl = DWC2_READ_4(hsotg, PCGCTL);
1492 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl);
1497 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
1498 pcgctl = DWC2_READ_4(hsotg, PCGCTL);
1500 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl);
1502 spin_unlock_irqrestore(&hsotg->lock, flags);
1506 spin_unlock_irqrestore(&hsotg->lock, flags);
1511 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
1517 spin_lock_irqsave(&hsotg->lock, flags);
1523 if (!hsotg->core_params->hibernation) {
1524 pcgctl = DWC2_READ_4(hsotg, PCGCTL);
1526 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl);
1527 spin_unlock_irqrestore(&hsotg->lock, flags);
1529 spin_lock_irqsave(&hsotg->lock, flags);
1532 hprt0 = dwc2_read_hprt0(hsotg);
1535 DWC2_WRITE_4(hsotg, HPRT0, hprt0);
1536 spin_unlock_irqrestore(&hsotg->lock, flags);
1540 spin_lock_irqsave(&hsotg->lock, flags);
1541 hprt0 = dwc2_read_hprt0(hsotg);
1543 DWC2_WRITE_4(hsotg, HPRT0, hprt0);
1544 hsotg->bus_suspended = 0;
1545 spin_unlock_irqrestore(&hsotg->lock, flags);
1550 dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1563 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1573 dev_err(hsotg->dev,
1585 dev_dbg(hsotg->dev,
1587 hprt0 = dwc2_read_hprt0(hsotg);
1589 DWC2_WRITE_4(hsotg, HPRT0, hprt0);
1593 dev_dbg(hsotg->dev,
1595 if (hsotg->bus_suspended)
1596 dwc2_port_resume(hsotg);
1600 dev_dbg(hsotg->dev,
1602 hprt0 = dwc2_read_hprt0(hsotg);
1604 DWC2_WRITE_4(hsotg, HPRT0, hprt0);
1608 dev_dbg(hsotg->dev,
1617 dev_dbg(hsotg->dev,
1619 hsotg->flags.b.port_connect_status_change = 0;
1624 dev_dbg(hsotg->dev,
1626 hsotg->flags.b.port_reset_change = 0;
1634 dev_dbg(hsotg->dev,
1636 hsotg->flags.b.port_enable_change = 0;
1645 dev_dbg(hsotg->dev,
1647 hsotg->flags.b.port_suspend_change = 0;
1651 dev_dbg(hsotg->dev,
1653 hsotg->flags.b.port_l1_change = 0;
1657 dev_dbg(hsotg->dev,
1659 hsotg->flags.b.port_over_current_change = 0;
1664 dev_err(hsotg->dev,
1671 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1685 dev_dbg(hsotg->dev, "GetHubStatus\n");
1690 dev_vdbg(hsotg->dev,
1692 hsotg->flags.d32);
1697 if (hsotg->flags.b.port_connect_status_change)
1699 if (hsotg->flags.b.port_enable_change)
1701 if (hsotg->flags.b.port_suspend_change)
1703 if (hsotg->flags.b.port_l1_change)
1705 if (hsotg
1707 if (hsotg->flags.b.port_over_current_change) {
1708 dev_warn(hsotg->dev, "Overcurrent change detected\n");
1713 dev_vdbg(hsotg->dev, "wPortChange=%04x\n", port_status);
1714 if (!hsotg->flags.b.port_connect_status) {
1728 hprt0 = DWC2_READ_4(hsotg, HPRT0);
1729 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
1755 if (hsotg->core_params->dma_desc_fs_enable) {
1760 if (hsotg->new_connection &&
1768 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
1769 hsotg->core_params->dma_desc_enable = 1;
1770 hcfg = DWC2_READ_4(hsotg, HCFG);
1772 DWC2_WRITE_4(hsotg, HCFG, hcfg);
1773 hsotg->new_connection = false;
1776 dev_vdbg(hsotg->dev, "wPortStatus=%04x\n", port_status);
1781 dev_dbg(hsotg->dev, "SetHubFeature\n");
1786 dev_dbg(hsotg->dev, "SetPortFeature\n");
1790 if (!hsotg->flags.b.port_connect_status) {
1803 dev_dbg(hsotg->dev,
1805 if (windex != hsotg->otg_port)
1807 dwc2_port_suspend(hsotg, windex);
1811 dev_dbg(hsotg->dev,
1813 hprt0 = dwc2_read_hprt0(hsotg);
1815 DWC2_WRITE_4(hsotg, HPRT0, hprt0);
1819 hprt0 = dwc2_read_hprt0(hsotg);
1820 dev_dbg(hsotg->dev,
1822 pcgctl = DWC2_READ_4(hsotg, PCGCTL);
1824 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl);
1826 DWC2_WRITE_4(hsotg, PCGCTL, 0);
1828 hprt0 = dwc2_read_hprt0(hsotg);
1837 if (!dwc2_hcd_is_b_host(hsotg)) {
1839 dev_dbg(hsotg->dev,
1841 DWC2_WRITE_4(hsotg, HPRT0, hprt0);
1847 DWC2_WRITE_4(hsotg, HPRT0, hprt0);
1848 hsotg->lx_state = DWC2_L0; /* Now back to On state */
1852 dev_dbg(hsotg->dev,
1858 hprt0 = dwc2_read_hprt0(hsotg);
1859 dev_dbg(hsotg->dev,
1863 DWC2_WRITE_4(hsotg, HPRT0, hprt0);
1868 dev_err(hsotg->dev,
1878 dev_dbg(hsotg->dev,
1887 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1889 u32 hfnum = DWC2_READ_4(hsotg, HFNUM);
1892 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
1898 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1900 return hsotg->op_state == OTG_STATE_B_HOST;
1904 dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, int iso_desc_count,
1924 dwc2_hcd_urb_free(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb,
1935 dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb,
1942 dev_dbg(hsotg->dev, "urb=%p, xfer=%p\n", urb, urb->priv);
1954 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1965 num_channels = hsotg->core_params->host_channels;
1966 dev_dbg(hsotg->dev, "\n");
1967 dev_dbg(hsotg->dev,
1969 dev_dbg(hsotg->dev, "HCD State:\n");
1970 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
1973 chan = hsotg->hc_ptr_array[i];
1974 dev_dbg(hsotg->dev, " Channel %d:\n", i);
1975 dev_dbg(hsotg->dev,
1978 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
1979 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
1980 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
1981 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
1983 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
1984 dev_dbg(hsotg->dev, " xfer_started: %d\n",
1986 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
1987 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
1989 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
1990 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
1991 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
1993 dev_dbg(hsotg->dev, " halt_pending: %d\n",
1995 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
1996 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
1997 dev_dbg(hsotg->dev, " complete_split: %d\n",
1999 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
2000 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
2001 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
2002 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
2003 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
2006 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n",
2007 DWC2_READ_4(hsotg, HFNUM));
2008 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n",
2009 DWC2_READ_4(hsotg, HCCHAR(i)));
2010 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n",
2011 DWC2_READ_4(hsotg, HCTSIZ(i)));
2012 dev_dbg(hsotg->dev, " hcint: 0x%08x\n",
2013 DWC2_READ_4(hsotg, HCINT(i)));
2014 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n",
2015 DWC2_READ_4(hsotg, HCINTMSK(i)));
2025 dev_dbg(hsotg->dev, " URB Info:\n");
2026 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
2029 dev_dbg(hsotg->dev,
2035 dev_dbg(hsotg->dev,
2038 dev_dbg(hsotg->dev,
2041 dev_dbg(hsotg->dev,
2044 dev_dbg(hsotg->dev,
2047 dev_dbg(hsotg->dev, " actual_length: %d\n",
2053 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
2054 hsotg->non_periodic_channels);
2055 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
2056 hsotg->periodic_channels);
2057 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
2058 np_tx_status = DWC2_READ_4(hsotg, GNPTXSTS);
2059 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
2061 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
2063 p_tx_status = DWC2_READ_4(hsotg, HPTXSTS);
2064 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
2066 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
2068 dwc2_hcd_dump_frrem(hsotg);
2070 dwc2_dump_global_registers(hsotg);
2071 dwc2_dump_host_registers(hsotg);
2072 dev_dbg(hsotg->dev,
2074 dev_dbg(hsotg->dev, "\n");
2082 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
2085 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
2086 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2087 hsotg->frrem_samples, hsotg->frrem_accum,
2088 hsotg->frrem_samples > 0 ?
2089 hsotg->frrem_accum / hsotg->frrem_samples : 0);
2090 dev_dbg(hsotg->dev, "\n");
2091 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
2092 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2093 hsotg->hfnum_7_samples,
2094 hsotg->hfnum_7_frrem_accum,
2095 hsotg->hfnum_7_samples > 0 ?
2096 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
2097 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
2098 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2099 hsotg->hfnum_0_samples,
2100 hsotg->hfnum_0_frrem_accum,
2101 hsotg->hfnum_0_samples > 0 ?
2102 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
2103 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
2104 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2105 hsotg->hfnum_other_samples,
2106 hsotg->hfnum_other_frrem_accum,
2107 hsotg->hfnum_other_samples > 0 ?
2108 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
2110 dev_dbg(hsotg->dev, "\n");
2111 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
2112 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2113 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
2114 hsotg->hfnum_7_samples_a > 0 ?
2115 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
2116 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
2117 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2118 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
2119 hsotg->hfnum_0_samples_a > 0 ?
2120 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
2121 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
2122 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2123 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
2124 hsotg->hfnum_other_samples_a > 0 ?
2125 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
2127 dev_dbg(hsotg->dev, "\n");
2128 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
2129 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2130 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
2131 hsotg->hfnum_7_samples_b > 0 ?
2132 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
2133 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
2134 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2135 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
2136 (hsotg->hfnum_0_samples_b > 0) ?
2137 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
2138 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
2139 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2140 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
2141 (hsotg->hfnum_other_samples_b > 0) ?
2142 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
2148 struct dwc2_hsotg *hsotg;
2152 void dwc2_host_start(struct dwc2_hsotg *hsotg)
2154 // struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2156 // hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2157 _dwc2_hcd_start(hsotg);
2160 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2162 // struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2172 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2175 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2176 dwc2_host_start(hsotg);
2184 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2189 dev_dbg(hsotg->dev, "USB RESET function called\n");
2191 spin_lock_irqsave(&hsotg->lock, flags);
2193 hprt0 = dwc2_read_hprt0(hsotg);
2195 DWC2_WRITE_4(hsotg, HPRT0, hprt0);
2196 hsotg->flags.b.port_reset_change = 1;
2198 dwc2_root_intr(hsotg->hsotg_sc);
2200 spin_unlock_irqrestore(&hsotg->lock, flags);
2219 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2225 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2228 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2229 hsotg, &hsotg->non_periodic_sched_waiting);
2230 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2231 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2232 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
2233 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
2234 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
2238 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
2241 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
2243 hsotg->hc_ptr_array[i] = NULL;
2248 if (hsotg->core_params->dma_enable > 0) {
2249 if (hsotg->status_buf) {
2250 usb_freemem(&hsotg->status_buf_usbdma);
2251 hsotg->status_buf = NULL;
2254 kmem_free(hsotg->status_buf,DWC2_HCD_STATUS_BUF_SIZE);
2255 hsotg->status_buf = NULL;
2258 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG);
2262 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg);
2263 DWC2_WRITE_4(hsotg, GINTMSK, 0);
2265 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
2266 dctl = DWC2_READ_4(hsotg, DCTL);
2268 DWC2_WRITE_4(hsotg, DCTL, dctl);
2271 if (hsotg->wq_otg) {
2272 if (!cancel_work_sync(&hsotg->wf_otg))
2273 flush_workqueue(hsotg->wq_otg);
2274 destroy_workqueue(hsotg->wq_otg);
2277 kmem_free(hsotg->core_params, sizeof(*hsotg->core_params));
2278 hsotg->core_params = NULL;
2279 callout_destroy(&hsotg->wkp_timer);
2282 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
2285 dwc2_disable_host_interrupts(hsotg);
2287 dwc2_hcd_free(hsotg);
2296 int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
2305 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
2309 dev_dbg(hsotg->dev, "hcfg=%08x\n", DWC2_READ_4(hsotg, HCFG));
2312 hsotg->frame_num_array = kmem_zalloc(sizeof(*hsotg->frame_num_array) *
2314 if (!hsotg->frame_num_array)
2316 hsotg->last_frame_num_array = kmem_zalloc(
2317 sizeof(*hsotg->last_frame_num_array) *
2319 if (!hsotg->last_frame_num_array)
2321 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
2324 spin_lock_init(&hsotg->lock);
2330 dwc2_disable_global_interrupts(hsotg);
2333 retval = dwc2_core_init(hsotg, true);
2339 hsotg->wq_otg = create_singlethread_workqueue("dwc2");
2340 if (!hsotg->wq_otg) {
2341 dev_err(hsotg->dev, "Failed to create workqueue\n");
2344 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
2346 callout_init(&hsotg->wkp_timer, CALLOUT_MPSAFE);
2347 callout_setfunc(&hsotg->wkp_timer, dwc2_wakeup_detected, hsotg);
2350 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
2351 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting);
2352 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
2355 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
2356 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
2357 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
2358 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
2364 INIT_LIST_HEAD(&hsotg->free_hc_list);
2365 num_channels = hsotg->core_params->host_channels;
2366 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
2373 hsotg->hc_ptr_array[i] = channel;
2376 if (hsotg->core_params->uframe_sched > 0)
2377 dwc2_hcd_init_usecs(hsotg);
2379 /* Initialize hsotg start work */
2380 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
2383 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
2391 hsotg->status_buf = NULL;
2392 if (hsotg->core_params->dma_enable > 0) {
2393 int error = usb_allocmem(hsotg->hsotg_sc->sc_bus.ub_dmatag,
2395 &hsotg->status_buf_usbdma);
2397 hsotg->status_buf = KERNADDR(&hsotg->status_buf_usbdma, 0);
2398 hsotg->status_buf_dma = DMAADDR(&hsotg->status_buf_usbdma, 0);
2401 hsotg->status_buf = kmem_zalloc(DWC2_HCD_STATUS_BUF_SIZE,
2405 if (!hsotg->status_buf)
2408 hsotg->otg_port = 1;
2409 hsotg->frame_list = NULL;
2410 hsotg->frame_list_dma = 0;
2411 hsotg->periodic_qh_count = 0;
2414 hsotg->lx_state = DWC2_L3;
2416 _dwc2_hcd_start(hsotg);
2418 dwc2_hcd_dump_state(hsotg);
2420 dwc2_enable_global_interrupts(hsotg);
2425 dwc2_hcd_release(hsotg);
2427 if (hsotg->core_params != NULL)
2428 kmem_free(hsotg->core_params, sizeof(*hsotg->core_params));
2431 if (hsotg->last_frame_num_array != NULL)
2432 kmem_free(hsotg->last_frame_num_array,
2433 sizeof(*hsotg->last_frame_num_array) * FRAME_NUM_ARRAY_SIZE);
2434 if (hsotg->frame_num_array != NULL)
2435 kmem_free(hsotg->frame_num_array,
2436 sizeof(*hsotg->frame_num_array) * FRAME_NUM_ARRAY_SIZE);
2439 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
2447 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
2451 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
2453 hcd = dwc2_hsotg_to_hcd(hsotg);
2454 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
2457 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
2461 hsotg->priv = NULL;
2463 dwc2_hcd_release(hsotg);
2466 kmem_free(hsotg->last_frame_num_array, sizeof(*hsotg->last_frame_num_array) * FRAME_NUM_ARRAY_SIZE);
2467 kmem_free(hsotg->frame_num_array, sizeof(*hsotg->frame_num_array) * FRAME_NUM_ARRAY_SIZE);
Indexes created Thu Oct 02 14:10:14 GMT 2025