Lines Matching refs:hsotg
97 static int dwc2_desc_list_alloc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
109 err = usb_allocmem(hsotg->hsotg_sc->sc_bus.ub_dmatag,
128 static void dwc2_desc_list_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
140 static int dwc2_frame_list_alloc(struct dwc2_hsotg *hsotg, gfp_t mem_flags)
144 if (hsotg->frame_list)
148 hsotg->frame_list_sz = 4 * FRLISTEN_64_SIZE;
149 hsotg->frame_list = NULL;
150 err = usb_allocmem(hsotg->hsotg_sc->sc_bus.ub_dmatag,
151 hsotg->frame_list_sz, 0, USBMALLOC_COHERENT, &hsotg->frame_list_usbdma);
154 hsotg->frame_list = KERNADDR(&hsotg->frame_list_usbdma, 0);
155 hsotg->frame_list_dma = DMAADDR(&hsotg->frame_list_usbdma, 0);
158 if (!hsotg->frame_list)
164 static void dwc2_frame_list_free(struct dwc2_hsotg *hsotg)
169 spin_lock_irqsave(&hsotg->lock, flags);
171 if (!hsotg->frame_list) {
172 spin_unlock_irqrestore(&hsotg->lock, flags);
176 frame_list_usbdma = hsotg->frame_list_usbdma;
177 hsotg->frame_list = NULL;
179 spin_unlock_irqrestore(&hsotg->lock, flags);
184 static void dwc2_per_sched_enable(struct dwc2_hsotg *hsotg, u32 fr_list_en)
189 spin_lock_irqsave(&hsotg->lock, flags);
191 hcfg = DWC2_READ_4(hsotg, HCFG);
194 spin_unlock_irqrestore(&hsotg->lock, flags);
198 DWC2_WRITE_4(hsotg, HFLBADDR, hsotg->frame_list_dma);
202 dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n");
203 DWC2_WRITE_4(hsotg, HCFG, hcfg);
205 spin_unlock_irqrestore(&hsotg->lock, flags);
208 static void dwc2_per_sched_disable(struct dwc2_hsotg *hsotg)
213 spin_lock_irqsave(&hsotg->lock, flags);
215 hcfg = DWC2_READ_4(hsotg, HCFG);
218 spin_unlock_irqrestore(&hsotg->lock, flags);
223 dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n");
224 DWC2_WRITE_4(hsotg, HCFG, hcfg);
226 spin_unlock_irqrestore(&hsotg->lock, flags);
233 static void dwc2_update_frame_list(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
239 if (!hsotg) {
240 printf("hsotg = %p\n", hsotg);
245 dev_err(hsotg->dev, "qh->channel = %p\n", qh->channel);
249 if (!hsotg->frame_list) {
250 dev_err(hsotg->dev, "hsotg->frame_list = %p\n",
251 hsotg->frame_list);
265 hsotg->frame_list[j] |= 1 << chan->hc_num;
267 hsotg->frame_list[j] &= ~(1 << chan->hc_num);
275 usb_syncmem(&hsotg->frame_list_usbdma, 0, hsotg->frame_list_sz,
295 static void dwc2_release_channel_ddma(struct dwc2_hsotg *hsotg,
301 if (hsotg->core_params->uframe_sched > 0)
302 hsotg->available_host_channels++;
304 hsotg->non_periodic_channels--;
306 dwc2_update_frame_list(hsotg, qh, 0);
307 hsotg->available_host_channels++;
317 dwc2_hc_cleanup(hsotg, chan);
318 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
334 * @hsotg: The HCD state structure for the DWC OTG controller
342 int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
348 dev_err(hsotg->dev,
354 retval = dwc2_desc_list_alloc(hsotg, qh, mem_flags);
360 if (!hsotg->frame_list) {
361 retval = dwc2_frame_list_alloc(hsotg, mem_flags);
365 dwc2_per_sched_enable(hsotg, HCFG_FRLISTEN_64);
373 dwc2_desc_list_free(hsotg, qh);
382 * @hsotg: The HCD state structure for the DWC OTG controller
388 void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
392 dwc2_desc_list_free(hsotg, qh);
401 spin_lock_irqsave(&hsotg->lock, flags);
403 dwc2_release_channel_ddma(hsotg, qh);
404 spin_unlock_irqrestore(&hsotg->lock, flags);
408 (hsotg->core_params->uframe_sched > 0 ||
409 !hsotg->periodic_channels) && hsotg->frame_list) {
410 dwc2_per_sched_disable(hsotg);
411 dwc2_frame_list_free(hsotg);
428 static u16 dwc2_calc_starting_frame(struct dwc2_hsotg *hsotg,
433 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
459 if (dwc2_micro_frame_num(hsotg->frame_number) >= 5) {
461 frame = dwc2_frame_num_inc(hsotg->frame_number,
465 frame = dwc2_frame_num_inc(hsotg->frame_number,
477 frame = dwc2_frame_num_inc(hsotg->frame_number, 2);
487 static u16 dwc2_recalc_initial_desc_idx(struct dwc2_hsotg *hsotg,
511 frame = dwc2_calc_starting_frame(hsotg, qh, &skip_frames);
522 qh->sched_frame = dwc2_calc_starting_frame(hsotg, qh,
538 static void dwc2_fill_host_isoc_dma_desc(struct dwc2_hsotg *hsotg,
576 static void dwc2_init_isoc_dma_desc(struct dwc2_hsotg *hsotg,
587 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
588 hsotg->frame_number);
600 dev_vdbg(hsotg->dev,
627 dwc2_fill_host_isoc_dma_desc(hsotg, qtd, qh,
684 static void dwc2_fill_host_dma_desc(struct dwc2_hsotg *hsotg,
735 static void dwc2_init_non_isoc_dma_desc(struct dwc2_hsotg *hsotg,
742 dev_vdbg(hsotg->dev, "%s(): qh=%p dma=%08lx len=%d\n", __func__, qh,
753 dev_vdbg(hsotg->dev, "qtd=%p\n", qtd);
761 dev_vdbg(hsotg->dev, "buf=%08lx len=%d\n",
769 dev_vdbg(hsotg->dev,
779 dwc2_fill_host_dma_desc(hsotg, chan, qtd, qh, n_desc);
780 dev_vdbg(hsotg->dev,
790 dev_vdbg(hsotg->dev, "n_desc=%d\n", n_desc);
801 dev_vdbg(hsotg->dev, "set IOC/EOL/A bits in desc %d (%p)\n",
809 dev_vdbg(hsotg->dev, "set A bit in desc 0 (%p)\n",
822 * @hsotg: The HCD state structure for the DWC OTG controller
838 void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
847 dwc2_init_non_isoc_dma_desc(hsotg, qh);
848 dwc2_hc_start_transfer_ddma(hsotg, chan);
851 dwc2_init_non_isoc_dma_desc(hsotg, qh);
852 dwc2_update_frame_list(hsotg, qh, 1);
853 dwc2_hc_start_transfer_ddma(hsotg, chan);
857 skip_frames = dwc2_recalc_initial_desc_idx(hsotg, qh);
858 dwc2_init_isoc_dma_desc(hsotg, qh, skip_frames);
861 dwc2_update_frame_list(hsotg, qh, 1);
871 dwc2_hc_start_transfer_ddma(hsotg, chan);
883 static int dwc2_cmpl_host_isoc_dma_desc(struct dwc2_hsotg *hsotg,
929 dwc2_host_complete(hsotg, qtd, 0);
930 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
952 static void dwc2_complete_isoc_xfer_ddma(struct dwc2_hsotg *hsotg,
994 dwc2_host_complete(hsotg, qtd, err);
997 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1013 dev_vdbg(hsotg->dev,
1023 rc = dwc2_cmpl_host_isoc_dma_desc(hsotg, chan, qtd, qh,
1039 cur_idx = dwc2_frame_list_idx(hsotg->frame_number);
1056 static int dwc2_update_non_isoc_urb_state_ddma(struct dwc2_hsotg *hsotg,
1070 dev_vdbg(hsotg->dev, "remain=%d dwc2_urb=%p\n", remain, urb);
1073 dev_err(hsotg->dev, "EIO\n");
1081 dev_vdbg(hsotg->dev, "Stall\n");
1085 dev_err(hsotg->dev, "Babble\n");
1089 dev_err(hsotg->dev, "XactErr\n");
1093 dev_err(hsotg->dev,
1102 dev_vdbg(hsotg->dev,
1127 dev_vdbg(hsotg->dev, "length=%d actual=%d\n", urb->length,
1138 static int dwc2_process_non_isoc_desc(struct dwc2_hsotg *hsotg,
1151 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1163 dev_vdbg(hsotg->dev,
1166 failed = dwc2_update_non_isoc_urb_state_ddma(hsotg, chan, qtd, dma_desc,
1173 dwc2_host_complete(hsotg, qtd, urb->status);
1174 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1175 dev_vdbg(hsotg->dev, "failed=%1x xfer_done=%1x status=%08x\n",
1187 dev_vdbg(hsotg->dev,
1193 dev_vdbg(hsotg->dev,
1200 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1212 static void dwc2_complete_non_isoc_xfer_ddma(struct dwc2_hsotg *hsotg,
1236 if (dwc2_process_non_isoc_desc(hsotg, chan, chnum, qtd,
1254 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1274 * @hsotg: The HCD state structure for the DWC OTG controller
1286 void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg,
1295 dwc2_complete_isoc_xfer_ddma(hsotg, chan, halt_status);
1309 dwc2_host_complete(hsotg, qtd,
1311 dwc2_hcd_qtd_unlink_and_free(hsotg,
1317 dwc2_hc_halt(hsotg, chan, halt_status);
1318 dwc2_release_channel_ddma(hsotg, qh);
1319 dwc2_hcd_qh_unlink(hsotg, qh);
1323 &hsotg->periodic_sched_assigned);
1340 dwc2_complete_non_isoc_xfer_ddma(hsotg, chan, chnum,
1342 dwc2_release_channel_ddma(hsotg, qh);
1343 dwc2_hcd_qh_unlink(hsotg, qh);
1350 dwc2_hcd_qh_add(hsotg, qh);
1354 tr_type = dwc2_hcd_select_transactions(hsotg);
1362 dwc2_hcd_queue_transactions(hsotg, tr_type);
Indexes created Mon Oct 27 08:10:08 GMT 2025