Lines Matching refs:hsotg
74 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
77 u16 curr_frame_number = hsotg->frame_number;
79 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
80 if (((hsotg->last_frame_num + 1) & HFNUM_MAX_FRNUM) !=
82 hsotg->frame_num_array[hsotg->frame_num_idx] =
84 hsotg->last_frame_num_array[hsotg->frame_num_idx] =
85 hsotg->last_frame_num;
86 hsotg->frame_num_idx++;
88 } else if (!hsotg->dumped_frame_num_array) {
91 dev_info(hsotg->dev, "Frame Last Frame\n");
92 dev_info(hsotg->dev, "----- ----------\n");
94 dev_info(hsotg->dev, "0x%04x 0x%04x\n",
95 hsotg->frame_num_array[i],
96 hsotg->last_frame_num_array[i]);
98 hsotg->dumped_frame_num_array = 1;
100 hsotg->last_frame_num = curr_frame_number;
104 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
132 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
139 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_SOF);
142 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
145 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
147 dwc2_track_missed_sofs(hsotg);
150 qh_entry = hsotg->periodic_sched_inactive.next;
151 while (qh_entry != &hsotg->periodic_sched_inactive) {
154 if (dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number))
160 &hsotg->periodic_sched_ready);
162 tr_type = dwc2_hcd_select_transactions(hsotg);
164 dwc2_hcd_queue_transactions(hsotg, tr_type);
172 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
178 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
180 grxsts = DWC2_READ_4(hsotg, GRXSTSP);
182 chan = hsotg->hc_ptr_array[chnum];
184 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
193 dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum);
194 dev_vdbg(hsotg->dev, " Count = %d\n", bcnt);
195 dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n",
198 dev_vdbg(hsotg->dev, " PStatus = %d\n", pktsts);
205 dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
218 dev_err(hsotg->dev,
230 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
232 dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
233 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
242 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
245 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
246 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
249 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
252 struct dwc2_core_params *params = hsotg->core_params;
260 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
263 hfir = DWC2_READ_4(hsotg, HFIR);
265 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
267 DWC2_WRITE_4(hsotg, HFIR, hfir);
272 hsotg->flags.b.port_reset_change = 1;
274 dwc2_root_intr(hsotg->hsotg_sc);
278 usbcfg = DWC2_READ_4(hsotg, GUSBCFG);
286 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg);
290 hcfg = DWC2_READ_4(hsotg, HCFG);
298 dev_vdbg(hsotg->dev,
304 DWC2_WRITE_4(hsotg, HCFG, hcfg);
309 dev_vdbg(hsotg->dev,
315 DWC2_WRITE_4(hsotg, HCFG, hcfg);
323 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg);
330 DWC2_WRITE_4(hsotg, HPRT0, *hprt0_modify);
331 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
335 hsotg->flags.b.port_reset_change = 1;
336 dwc2_root_intr(hsotg->hsotg_sc);
346 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
351 dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
353 hprt0 = DWC2_READ_4(hsotg, HPRT0);
368 DWC2_WRITE_4(hsotg, HPRT0, hprt0_modify | HPRT0_CONNDET);
370 dev_vdbg(hsotg->dev,
373 dwc2_hcd_connect(hsotg);
386 DWC2_WRITE_4(hsotg, HPRT0, hprt0_modify | HPRT0_ENACHG);
387 dev_vdbg(hsotg->dev,
391 hsotg->new_connection = true;
392 dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
394 hsotg->flags.b.port_enable_change = 1;
395 if (hsotg->core_params->dma_desc_fs_enable) {
398 hsotg->core_params->dma_desc_enable = 0;
399 hsotg->new_connection = false;
400 hcfg = DWC2_READ_4(hsotg, HCFG);
402 DWC2_WRITE_4(hsotg, HCFG, hcfg);
409 DWC2_WRITE_4(hsotg, HPRT0, hprt0_modify | HPRT0_OVRCURRCHG);
410 dev_vdbg(hsotg->dev,
413 hsotg->flags.b.port_over_current_change = 1;
416 if (hsotg->flags.b.port_connect_status_change ||
417 hsotg->flags.b.port_enable_change ||
418 hsotg->flags.b.port_over_current_change)
419 dwc2_root_intr(hsotg->hsotg_sc);
431 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
439 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum));
479 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
486 int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
491 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
497 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
509 dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
523 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
525 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
526 dev_vdbg(hsotg
527 (DWC2_READ_4(hsotg, HCTSIZ(chnum)) & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT);
528 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length);
529 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length);
530 dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read,
541 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
545 u32 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum));
572 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
588 len = dwc2_get_actual_xfer_length(hsotg,
593 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n",
632 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
637 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n",
657 hsotg->core_params->dma_enable > 0) {
664 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
674 dwc2_host_complete(hsotg, qtd, 0);
690 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
697 dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__,
698 hsotg, qh, free_qtd);
701 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
714 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
722 dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
728 * @hsotg: The HCD state structure
738 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
748 dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n",
762 dev_vdbg(hsotg->dev,
765 dwc2_host_complete(hsotg, qtd, -EPROTO);
776 dev_vdbg(hsotg->dev, " Complete URB with I/O error\n");
778 dwc2_host_complete(hsotg, qtd, -EIO);
785 dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
795 dwc2_hc_cleanup(hsotg, chan);
796 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
798 if (hsotg->core_params->uframe_sched > 0) {
799 hsotg->available_host_channels++;
804 hsotg->non_periodic_channels--;
817 haintmsk = DWC2_READ_4(hsotg, HAINTMSK);
819 DWC2_WRITE_4(hsotg, HAINTMSK, haintmsk);
822 tr_type = dwc2_hcd_select_transactions(hsotg);
824 dwc2_hcd_queue_transactions(hsotg, tr_type);
837 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
842 dev_vdbg(hsotg->dev, "%s()\n", __func__);
844 if (hsotg->core_params->dma_enable > 0) {
846 dev_vdbg(hsotg->dev, "DMA enabled\n");
847 dwc2_release_channel(hsotg, chan, qtd, halt_status);
852 dwc2_hc_halt(hsotg, chan, halt_status);
857 dev_vdbg(hsotg->dev, "Halt on queue\n");
860 dev_vdbg(hsotg->dev, "control/bulk\n");
866 gintmsk = DWC2_READ_4(hsotg, GINTMSK);
868 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk);
870 dev_vdbg(hsotg->dev, "isoc/intr\n");
878 &hsotg->periodic_sched_assigned);
885 gintmsk = DWC2_READ_4(hsotg, GINTMSK);
887 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk);
897 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
902 dev_vdbg(hsotg->dev, "%s()\n", __func__);
912 dev_vdbg(hsotg->dev, "got NYET\n");
932 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
938 dwc2_release_channel(hsotg, chan, qtd, halt_status);
947 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
952 u32 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum));
958 dwc2_release_channel(hsotg, chan, qtd, halt_status);
961 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
964 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
975 len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
986 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
1005 dwc2_host_complete(hsotg, qtd, 0);
1006 dwc2_release_channel(hsotg, chan, qtd,
1009 dwc2_release_channel(hsotg, chan, qtd,
1020 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
1030 dev_vdbg(hsotg->dev,
1039 if (hsotg->core_params->dma_desc_enable > 0) {
1040 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
1050 hsotg->core_params->dma_enable > 0) {
1052 dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
1069 dev_vdbg(hsotg->dev,
1074 urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1078 dev_vdbg(hsotg->dev,
1081 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1087 dev_vdbg(hsotg->dev, " Control transfer complete\n");
1090 dwc2_host_complete(hsotg, qtd, urb->status);
1095 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1099 dev_vdbg(hsotg->dev, " Bulk transfer complete\n");
1100 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1103 dwc2_host_complete(hsotg, qtd, urb->status);
1109 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1110 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1114 dev_vdbg(hsotg->dev, " Interrupt transfer complete\n");
1115 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1123 dwc2_host_complete(hsotg, qtd, urb->status);
1129 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1130 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1135 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n");
1136 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1138 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1144 disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1151 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1158 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1161 if (hsotg->core_params->dma_desc_enable > 0) {
1162 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1173 dwc2_host_complete(hsotg, qtd, -EPIPE);
1177 dwc2_host_complete(hsotg, qtd, -EPIPE);
1189 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1192 disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1201 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1207 u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1211 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1217 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
1235 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1237 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
1239 dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n",
1240 (DWC2_READ_4(hsotg, HCTSIZ(chnum)) & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT);
1241 dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet);
1242 dev_vdbg(hsotg->dev, " bytes_transferred %d\n",
1244 dev_vdbg(hsotg->dev, " urb->actual_length %d\n",
1246 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n",
1254 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1259 dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__);
1264 dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__);
1269 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1294 chan->qh->nak_frame = dwc2_hcd_get_frame_number(hsotg);
1303 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1310 if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) {
1328 if (hsotg->core_params->dma_enable > 0 && !chan->ep_is_in) {
1336 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1338 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1349 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1353 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1357 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1362 disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1370 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1377 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1388 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1431 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1439 disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1449 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1454 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1463 hsotg->core_params->dma_enable > 0) {
1469 dwc2_host_complete(hsotg, qtd, 0);
1470 dwc2_release_channel(hsotg, chan, qtd,
1473 dwc2_release_channel(hsotg, chan, qtd,
1481 int frnum = dwc2_hcd_get_frame_number(hsotg);
1500 dwc2_halt_channel(hsotg, chan, qtd,
1507 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1514 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1516 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1522 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1525 disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1532 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1536 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1539 // dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1541 if (hsotg->core_params->dma_desc_enable > 0) {
1542 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1548 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1549 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1553 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1555 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1559 disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1566 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1572 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1578 // dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1583 u32 hcchar = DWC2_READ_4(hsotg, HCCHAR(chnum));
1584 u32 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chnum));
1585 u32 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum));
1586 u32 hc_dma = DWC2_READ_4(hsotg, HCDMA(chnum));
1588 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1589 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1590 dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1591 dev_err(hsotg->dev, " Device address: %d\n",
1593 dev_err(hsotg->dev, " Endpoint: %d, %s\n",
1615 dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype);
1632 dev_err(hsotg->dev, " Speed: %s\n", speed);
1634 dev_err(hsotg->dev, " Max packet size: %d\n",
1636 dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length);
1637 dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
1639 dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
1641 dev_err(hsotg->dev, " Interval: %d\n", urb->interval);
1645 if (hsotg->core_params->dma_desc_enable > 0) {
1646 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1651 dwc2_host_complete(hsotg, qtd, -EIO);
1658 dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1661 disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1668 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1672 dev_dbg(hsotg->dev,
1675 // dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1677 if (hsotg->core_params->dma_desc_enable > 0) {
1678 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1689 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1691 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1700 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1706 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1712 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1714 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1720 disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1727 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1734 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1737 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1744 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1747 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1749 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1753 disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1760 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1764 dev_dbg(hsotg->dev,
1770 dev_err(hsotg->dev,
1774 // dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1775 disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1785 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1800 hcchar = DWC2_READ_4(hsotg, HCCHAR(chnum));
1801 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum));
1802 hcintmsk = DWC2_READ_4(hsotg, HCINTMSK(chnum));
1803 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chnum));
1804 dev_dbg(hsotg->dev,
1807 dev_dbg(hsotg->dev,
1810 dev_dbg(hsotg->dev,
1814 dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1816 dev_warn(hsotg->dev,
1827 hcchar = DWC2_READ_4(hsotg, HCCHAR(chnum));
1829 dev_warn(hsotg->dev,
1833 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1845 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1853 dev_vdbg(hsotg->dev,
1861 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
1871 hsotg->core_params->dma_desc_enable <= 0)) {
1872 if (hsotg->core_params->dma_desc_enable > 0)
1873 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1882 dwc2_release_channel(hsotg, chan, qtd,
1887 hcintmsk = DWC2_READ_4(hsotg, HCINTMSK(chnum));
1898 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1899 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1901 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1903 hsotg->core_params->dma_desc_enable <= 0) {
1907 dev_vdbg(hsotg->dev,
1911 dev_vdbg(hsotg->dev,
1921 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1923 hsotg->core_params->dma_desc_enable > 0) {
1924 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1926 hsotg->core_params->dma_desc_enable > 0) {
1927 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1929 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1931 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1940 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1950 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1960 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1970 dev_dbg(hsotg->dev,
1973 dwc2_halt_channel(hsotg, chan, qtd,
1976 dev_err(hsotg->dev,
1979 dev_err(hsotg->dev,
1982 DWC2_READ_4(hsotg, GINTSTS));
1987 dev_info(hsotg->dev,
1993 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1995 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1996 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
2011 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
2016 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
2019 if (hsotg->core_params->dma_enable > 0) {
2020 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
2022 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
2024 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
2047 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
2053 chan = hsotg->hc_ptr_array[chnum];
2055 hcint = DWC2_READ_4(hsotg, HCINT(chnum));
2056 hcintmsk = DWC2_READ_4(hsotg, HCINTMSK(chnum));
2058 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
2059 DWC2_WRITE_4(hsotg, HCINT(chnum), hcint);
2064 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
2066 dev_vdbg(hsotg->dev,
2071 DWC2_WRITE_4(hsotg, HCINT(chnum), hcint);
2086 if (hsotg->core_params->dma_desc_enable > 0)
2087 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
2090 dwc2_release_channel(hsotg, chan, NULL,
2100 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
2102 dev_dbg(hsotg->dev,
2106 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
2114 if (hsotg->core_params->dma_enable <= 0) {
2120 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2130 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2135 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2140 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2145 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2150 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2155 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2160 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2165 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2170 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2175 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2190 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2195 haint = DWC2_READ_4(hsotg, HAINT);
2197 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2199 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2202 for (i = 0; i < hsotg->core_params->host_channels; i++) {
2204 dwc2_hc_n_intr(hsotg, i);
2209 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2214 if (!dwc2_is_controller_alive(hsotg)) {
2215 dev_warn(hsotg->dev, "Controller is dead\n");
2219 KASSERT(mutex_owned(&hsotg->lock));
2222 if (dwc2_is_host_mode(hsotg)) {
2223 gintsts = dwc2_read_core_intr(hsotg);
2240 dev_vdbg(hsotg->dev,
2245 dwc2_sof_intr(hsotg);
2247 dwc2_rx_fifo_level_intr(hsotg);
2249 dwc2_np_tx_fifo_empty_intr(hsotg);
2251 dwc2_port_intr(hsotg);
2253 dwc2_hc_intr(hsotg);
2255 dwc2_perio_tx_fifo_empty_intr(hsotg);
2258 dev_vdbg(hsotg->dev,
2260 dev_vdbg(hsotg->dev,
2262 DWC2_READ_4(hsotg, GINTSTS),
2263 DWC2_READ_4(hsotg, GINTMSK));
Indexes created Mon Oct 20 03:09:53 GMT 2025