Lines Matching defs:hsotg
75 * @hsotg: The HCD state structure for the DWC OTG controller
81 static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
86 dev_vdbg(hsotg->dev, "%s()\n", __func__);
89 qh->hsotg = hsotg;
102 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
104 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
109 dev_vdbg(hsotg->dev,
125 qh->usecs = dwc2_calc_bus_time(hsotg, qh->do_split ?
131 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
133 qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number,
141 hprt = DWC2_READ_4(hsotg, HPRT0);
150 dev_dbg(hsotg->dev, "interval=%d\n", qh->interval);
153 dev_vdbg(hsotg->dev, "DWC OTG HCD QH Initialized\n");
154 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - qh = %p\n", qh);
155 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Device Address = %d\n",
157 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Endpoint %d, %s\n",
179 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Speed = %s\n", speed);
199 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Type = %s\n", type);
203 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - usecs = %d\n",
205 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - interval = %d\n",
213 * @hsotg: The HCD state structure for the DWC OTG controller
220 struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
224 struct dwc2_softc *sc = hsotg->hsotg_sc;
236 dwc2_qh_init(hsotg, qh, urb);
238 if (hsotg->core_params->dma_desc_enable > 0 &&
239 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
240 dwc2_hcd_qh_free(hsotg, qh);
250 * @hsotg: HCD instance
258 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
260 struct dwc2_softc *sc = hsotg->hsotg_sc;
273 dwc2_hcd_qh_free_ddma(hsotg, qh);
286 * @hsotg: The HCD state structure for the DWC OTG controller
290 static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
300 num_channels = hsotg->core_params->host_channels;
301 if (hsotg->periodic_channels + hsotg->non_periodic_channels <
303 && hsotg->periodic_channels < num_channels - 1) {
306 dev_dbg(hsotg->dev,
309 hsotg->periodic_channels, hsotg->non_periodic_channels);
320 * @hsotg: The HCD state structure for the DWC OTG controller
328 static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
350 if (hsotg->periodic_usecs > max_claimed_usecs) {
351 dev_err(hsotg->dev,
353 __func__, hsotg->periodic_usecs, qh->usecs);
362 * track the total use in hsotg->frame_usecs
370 void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg)
375 hsotg->frame_usecs[i] = max_uframe_usecs[i];
378 static int dwc2_find_single_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
384 /* At the start hsotg->frame_usecs[i] = max_uframe_usecs[i] */
385 if (utime <= hsotg->frame_usecs[i]) {
386 hsotg->frame_usecs[i] -= utime;
397 static int dwc2_find_multi_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
407 if (hsotg->frame_usecs[i] <= 0)
414 xtime = hsotg->frame_usecs[i];
420 if (xtime + hsotg->frame_usecs[j] < utime) {
421 if (hsotg->frame_usecs[j] <
428 t_left -= hsotg->frame_usecs[k];
431 hsotg->frame_usecs[k]
433 hsotg->frame_usecs[k] = -t_left;
437 hsotg->frame_usecs[k];
438 hsotg->frame_usecs[k] = 0;
443 xtime += hsotg->frame_usecs[j];
446 hsotg->frame_usecs[j] == max_uframe_usecs[j])
453 static int dwc2_find_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
459 ret = dwc2_find_single_uframe(hsotg, qh);
465 ret = dwc2_find_multi_uframe(hsotg, qh);
475 * @hsotg: The HCD state structure for the DWC OTG controller
480 static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
488 max_channel_xfer_size = hsotg->core_params->max_transfer_size;
491 dev_err(hsotg->dev,
504 * @hsotg: The HCD state structure for the DWC OTG controller
510 static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
514 if (hsotg->core_params->uframe_sched > 0) {
517 status = dwc2_find_uframe(hsotg, qh);
532 status = dwc2_periodic_channel_available(hsotg);
534 dev_info(hsotg->dev,
540 status = dwc2_check_periodic_bandwidth(hsotg, qh);
544 dev_dbg(hsotg->dev,
550 status = dwc2_check_max_xfer_size(hsotg, qh);
552 dev_dbg(hsotg->dev,
558 if (hsotg->core_params->dma_desc_enable > 0)
560 list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
564 &hsotg->periodic_sched_inactive);
566 if (hsotg->core_params->uframe_sched <= 0)
568 hsotg->periodic_channels++;
571 hsotg->periodic_usecs += qh->usecs;
580 * @hsotg: The HCD state structure for the DWC OTG controller
583 static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
591 hsotg
593 if (hsotg->core_params->uframe_sched > 0) {
595 hsotg->frame_usecs[i] += qh->frame_usecs[i];
600 hsotg->periodic_channels--;
628 struct dwc2_hsotg *hsotg = qh->hsotg;
631 spin_lock_irqsave(&hsotg->lock, flags);
643 &hsotg->non_periodic_sched_inactive);
645 tr_type = dwc2_hcd_select_transactions(hsotg);
647 dwc2_hcd_queue_transactions(hsotg, tr_type);
650 spin_unlock_irqrestore(&hsotg->lock, flags);
658 * @hsotg: The HCD state structure for the DWC OTG controller
663 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
669 dev_vdbg(hsotg->dev, "%s()\n", __func__);
675 if (!dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number) &&
676 !hsotg->frame_number) {
677 dev_dbg(hsotg->dev,
679 qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number,
687 &hsotg->non_periodic_sched_waiting);
695 &hsotg->non_periodic_sched_inactive);
700 status = dwc2_schedule_periodic(hsotg, qh);
703 if (!hsotg->periodic_qh_count) {
704 intr_mask = DWC2_READ_4(hsotg, GINTMSK);
706 DWC2_WRITE_4(hsotg, GINTMSK, intr_mask);
708 hsotg->periodic_qh_count++;
717 * @hsotg: The HCD state structure
720 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
724 dev_vdbg(hsotg->dev, "%s()\n", __func__);
734 if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry)
735 hsotg->non_periodic_qh_ptr =
736 hsotg->non_periodic_qh_ptr->next;
741 dwc2_deschedule_periodic(hsotg, qh);
742 hsotg->periodic_qh_count--;
743 if (!hsotg->periodic_qh_count) {
744 intr_mask = DWC2_READ_4(hsotg, GINTMSK);
746 DWC2_WRITE_4(hsotg, GINTMSK, intr_mask);
753 static void dwc2_sched_periodic_split(struct dwc2_hsotg *hsotg,
798 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
804 dev_vdbg(hsotg->dev, "%s()\n", __func__);
807 dwc2_hcd_qh_unlink(hsotg, qh);
810 dwc2_hcd_qh_add(hsotg, qh);
814 frame_number = dwc2_hcd_get_frame_number(hsotg);
817 dwc2_sched_periodic_split(hsotg, qh, frame_number,
827 dwc2_hcd_qh_unlink(hsotg, qh);
834 if ((hsotg->core_params->uframe_sched > 0 &&
836 (hsotg->core_params->uframe_sched <= 0 &&
838 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
840 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_inactive);
877 * @hsotg: The DWC HCD structure
886 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
890 KASSERT(mutex_owned(&hsotg->lock));
894 dev_err(hsotg->dev, "%s: Invalid QH\n", __func__);
899 retval = dwc2_hcd_qh_add(hsotg, qh);
911 void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
915 struct dwc2_softc *sc = hsotg->hsotg_sc;
926 static u32 dwc2_calc_bus_time(struct dwc2_hsotg *hsotg, int speed, int is_in,
976 dev_warn(hsotg->dev, "Unknown device speed\n");
Indexes created Tue Sep 30 20:09:53 GMT 2025