Lines Matching refs:ah
21 #include "ah.h"
40 ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac)
42 struct ath_hal_5212 *ahp = AH5212(ah);
48 ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *mac)
50 struct ath_hal_5212 *ahp = AH5212(ah);
57 ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mask)
59 struct ath_hal_5212 *ahp = AH5212(ah);
65 ar5212SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)
67 struct ath_hal_5212 *ahp = AH5212(ah);
72 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
73 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
81 ar5212SetRegulatoryDomain(struct ath_hal *ah,
86 if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {
90 if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {
95 if (ath_hal_eepromWrite(ah, AR_EEPROM_REG_DOMAIN, regDomain)) {
96 HALDEBUG(ah, HAL_DEBUG_ANY,
99 AH_PRIVATE(ah)->ah_currentRD = regDomain;
117 ar5212GetWirelessModes(struct ath_hal *ah)
121 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
123 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
125 if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)
127 if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)
130 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
132 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
133 AH_PRIVATE(ah)->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {
135 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
137 if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)
139 if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)
151 ar5212EnableRfKill(struct ath_hal *ah)
153 uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;
161 ath_hal_gpioCfgInput(ah, select);
162 OS_REG_SET_BIT(ah, AR_PHY(0), 0x00002000);
171 ath_hal_gpioSetIntr(ah, select,
172 (ath_hal_gpioGet(ah, select) == polarity ? !polarity : polarity));
179 ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
193 bits = OS_REG_READ(ah, AR_PCICFG);
194 if (IS_2417(ah)) {
211 OS_REG_WRITE(ah, AR_PCICFG, bits);
221 ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
223 struct ath_hal_5212 *ahp = AH5212(ah);
227 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
228 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
236 ar5212GetTsf64(struct ath_hal *ah)
241 low1 = OS_REG_READ(ah, AR_TSF_L32);
242 u32 = OS_REG_READ(ah, AR_TSF_U32);
243 low2 = OS_REG_READ(ah, AR_TSF_L32);
264 ar5212GetTsf32(struct ath_hal *ah)
266 return OS_REG_READ(ah, AR_TSF_L32);
273 ar5212ResetTsf(struct ath_hal *ah)
276 uint32_t val = OS_REG_READ(ah, AR_BEACON);
278 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
286 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
295 ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *rs)
297 HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
315 reg = OS_REG_READ(ah, AR_STA_ID1);
317 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
319 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
327 ar5212GetRandomSeed(struct ath_hal *ah)
331 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
334 return (OS_REG_READ(ah, AR_TSF_U32) ^
335 OS_REG_READ(ah, AR_TSF_L32) ^ nf);
342 ar5212DetectCardPresent(struct ath_hal *ah)
352 v = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
355 return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
356 AH_PRIVATE(ah)->ah_macRev == macRev);
360 ar5212EnableMibCounters(struct ath_hal *ah)
363 OS_REG_WRITE(ah, AR_MIBC,
368 ar5212DisableMibCounters(struct ath_hal *ah)
370 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC | AR_MIBC_CMC);
377 ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats)
379 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
380 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);
381 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);
382 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);
383 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);
390 ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah)
399 ar5212GetCurRssi(struct ath_hal *ah)
401 return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff);
405 ar5212GetDefAntenna(struct ath_hal *ah)
407 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
411 ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna)
413 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
417 ar5212GetAntennaSwitch(struct ath_hal *ah)
419 return AH5212(ah)->ah_antControl;
423 ar5212SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING setting)
425 struct ath_hal_5212 *ahp = AH5212(ah);
426 const HAL_CHANNEL_INTERNAL *ichan = AH_PRIVATE(ah)->ah_curchan;
434 return ar5212SetAntennaSwitchInternal(ah, setting, ichan);
438 ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah)
444 ar5212SetSifsTime(struct ath_hal *ah, u_int us)
446 struct ath_hal_5212 *ahp = AH5212(ah);
448 if (us > ath_hal_mac_usec(ah, 0xffff)) {
449 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",
455 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us-2));
462 ar5212GetSifsTime(struct ath_hal *ah)
464 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff;
465 return ath_hal_mac_usec(ah, clks)+2; /* convert from system clocks */
469 ar5212SetSlotTime(struct ath_hal *ah, u_int us)
471 struct ath_hal_5212 *ahp = AH5212(ah);
473 if (us < HAL_SLOT_TIME_6 || us > ath_hal_mac_usec(ah, 0xffff)) {
474 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",
480 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath_hal_mac_clks(ah, us));
487 ar5212GetSlotTime(struct ath_hal *ah)
489 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff;
490 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
494 ar5212SetAckTimeout(struct ath_hal *ah, u_int us)
496 struct ath_hal_5212 *ahp = AH5212(ah);
498 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
499 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",
505 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
506 AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));
513 ar5212GetAckTimeout(struct ath_hal *ah)
515 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
516 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
520 ar5212GetAckCTSRate(struct ath_hal *ah)
522 return ((AH5212(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);
526 ar5212SetAckCTSRate(struct ath_hal *ah, u_int high)
528 struct ath_hal_5212 *ahp = AH5212(ah);
531 OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
534 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
541 ar5212SetCTSTimeout(struct ath_hal *ah, u_int us)
543 struct ath_hal_5212 *ahp = AH5212(ah);
545 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
546 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",
552 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
553 AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));
560 ar5212GetCTSTimeout(struct ath_hal *ah)
562 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);
563 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
568 ar5212SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
570 struct ath_hal_5212 *ahp = AH5212(ah);
574 OS_REG_WRITE(ah, AR_DCM_A, keyidx);
575 OS_REG_WRITE(ah, AR_DCM_D, en ? AR_DCM_D_EN : 0);
583 ar5212SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
588 AH_PRIVATE(ah)->ah_coverageClass = coverageclass;
591 if (AH_PRIVATE(ah)->ah_coverageClass == 0)
595 if (!IS_CHAN_A(AH_PRIVATE(ah)->ah_curchan))
599 clkRate = ath_hal_mac_clks(ah, 1);
604 if (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) {
607 } else if (IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan)) {
624 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot);
625 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs);
626 OS_REG_WRITE(ah, AR_TIME_OUT,
633 ar5212SetPCUConfig(struct ath_hal *ah)
635 ar5212SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);
645 ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode)
648 struct ath_hal_5212 *ahp = AH5212(ah);
649 return ath_hal_eepromGetFlag(ah, AR_EEP_32KHZCRYSTAL) &&
663 ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode)
665 if (ar5212Use32KHzclock(ah, opmode)) {
671 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
672 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
673 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18);
674 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
675 OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */
676 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 1);
678 if (IS_2413(ah) || IS_5413(ah) || IS_2417(ah)) {
679 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x26);
680 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0d);
681 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x07);
682 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x3f);
684 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x2);
686 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x0a);
687 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0c);
688 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x03);
689 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x20);
690 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x3);
693 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x0);
694 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
696 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32MHz TSF inc */
698 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
699 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);
701 if (IS_2417(ah))
702 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0a);
703 else if (IS_HB63(ah))
704 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x32);
706 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
707 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);
708 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);
709 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
710 IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2417(ah) ? 0x14 : 0x18);
711 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
712 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);
720 ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode)
722 if (ar5212Use32KHzclock(ah, opmode)) {
724 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0);
725 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
727 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */
728 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
729 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);
734 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
735 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);
736 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
737 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);
738 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);
739 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
740 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18);
749 ar5212GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
775 ar5212GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
778 #define MACVERSION(ah) AH_PRIVATE(ah)->ah_macVersion
779 struct ath_hal_5212 *ahp = AH5212(ah);
780 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
819 return MACVERSION(ah) > AR_SREV_VERSION_VENICE ||
820 (MACVERSION(ah) == AR_SREV_VERSION_VENICE &&
821 AH_PRIVATE(ah)->ah_macRev >= 8) ? HAL_OK : HAL_ENOTSUPP;
831 *result = AH_PRIVATE(ah)->ah_diagreg;
844 return ath_hal_eepromGetFlag(ah, AR_EEP_AMODE) ?
847 return (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) ||
848 ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) ?
888 ani = ar5212AniGetCurrentState(ah);
902 return ath_hal_getcapability(ah, type, capability, result);
908 ar5212SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
912 struct ath_hal_5212 *ahp = AH5212(ah);
913 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
932 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
936 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
941 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
951 AH_PRIVATE(ah)->ah_diagreg = setting;
952 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
975 OS_REG_WRITE(ah, AR_TPC, ahp->ah_macTPC);
988 ar5212AniControl(ah, cmds[capability], setting) :
1001 return ath_hal_setcapability(ah, type, capability,
1008 ar5212GetDiagState(struct ath_hal *ah, int request,
1012 struct ath_hal_5212 *ahp = AH5212(ah);
1015 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))
1023 return ath_hal_eepromDiag(ah, request,
1039 *result = ar5212AniGetCurrentState(ah);
1044 *result = ar5212AniGetCurrentStats(ah);
1051 ar5212AniControl(ah, ((const uint32_t *)args)[0],
1062 ar5212AniGetCurrentState(ah);
1071 return ar5212AniSetParams(ah, args, args);
1084 ar5212IsNFCalInProgress(struct ath_hal *ah)
1086 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)
1099 ar5212WaitNFCalComplete(struct ath_hal *ah, int i)
1106 if (! ar5212IsNFCalInProgress(ah))
Indexes created Wed Oct 22 13:09:56 GMT 2025