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Lines Matching defs:ads

679 	struct ar5212_desc *ads = AR5212DESC(ds);
693 	ads->ds_ctl0 = (pktLen & AR_FrameLen)
700 	ads->ds_ctl1 = (type << AR_FrmType_S)
706 	ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0)
709 	ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S)
713 		ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
714 		ads->ds_ctl0 |= AR_DestIdxValid;
724 		ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
727 		ads->ds_ctl2 |= SM(rtsctsDuration, AR_RTSCTSDuration);
728 		ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S);
740 	struct ar5212_desc *ads = AR5212DESC(ds);
744 		ads->ds_ctl2 |= SM(txTries1, AR_XmitDataTries1)
747 		ads->ds_ctl3 |= (txRate1 << AR_XmitRate1_S);
751 		ads->ds_ctl2 |= SM(txTries2, AR_XmitDataTries2)
754 		ads->ds_ctl3 |= (txRate2 << AR_XmitRate2_S);
758 		ads->ds_ctl2 |= SM(txTries3, AR_XmitDataTries3)
761 		ads->ds_ctl3 |= (txRate3 << AR_XmitRate3_S);
769 	struct ar5212_desc *ads = AR5212DESC(ds);
772 	ads->ds_ctl0 |= __bswap32(AR_TxInterReq);
774 	ads->ds_ctl0 |= AR_TxInterReq;
783 	struct ar5212_desc *ads = AR5212DESC(ds);
792 		ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_More);
799 		ads->ds_ctl0 = 0;
800 		ads->ds_ctl1 = segLen;
802 		ads->ds_ctl2 = __bswap32(AR5212DESC_CONST(ds0)->ds_ctl2);
803 		ads->ds_ctl3 = __bswap32(AR5212DESC_CONST(ds0)->ds_ctl3);
805 		ads->ds_ctl2 = AR5212DESC_CONST(ds0)->ds_ctl2;
806 		ads->ds_ctl3 = AR5212DESC_CONST(ds0)->ds_ctl3;
812 		ads->ds_ctl0 = 0;
813 		ads->ds_ctl1 = segLen | AR_More;
814 		ads->ds_ctl2 = 0;
815 		ads->ds_ctl3 = 0;
817 	ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
843 	struct ar5212_desc *ads = AR5212DESC(ds);
846 	if ((ads->ds_txstatus1 & __bswap32(AR_Done)) == 0)
851 	if ((ads->ds_txstatus1 & AR_Done) == 0)
856 	ts->ts_seqnum = MS(ads->ds_txstatus1, AR_SeqNum);
857 	ts->ts_tstamp = MS(ads->ds_txstatus0, AR_SendTimestamp);
859 	if ((ads->ds_txstatus0 & AR_FrmXmitOK) == 0) {
860 		if (ads->ds_txstatus0 & AR_ExcessiveRetries)
862 		if (ads->ds_txstatus0 & AR_Filtered)
864 		if (ads->ds_txstatus0 & AR_FIFOUnderrun)
871 	ts->ts_finaltsi = MS(ads->ds_txstatus1, AR_FinalTSIndex);
874 		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate0);
877 		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate1) |
881 		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate2) |
885 		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate3) |
889 	ts->ts_rssi = MS(ads->ds_txstatus1, AR_AckSigStrength);
890 	ts->ts_shortretry = MS(ads->ds_txstatus0, AR_RTSFailCnt);
891 	ts->ts_longretry = MS(ads->ds_txstatus0, AR_DataFailCnt);
904 	case 3: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries2);
906 	case 2: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries1);
908 	case 1: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries0);
910 	ts->ts_virtcol = MS(ads->ds_txstatus0, AR_VirtCollCnt);
911 	ts->ts_antenna = (ads->ds_txstatus1 & AR_XmitAtenna ? 2 : 1);