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Lines Matching refs:qi

124 	HAL_TX_QUEUE_INFO *qi;
176 qi = &ahp->ah_txq[q];
177 if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
182 OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
183 qi->tqi_type = type;
185 qi->tqi_qflags = defqflags;
186 qi->tqi_aifs = INIT_AIFS;
187 qi->tqi_cwmin = HAL_TXQ_USEDEFAULT; /* NB: do at reset */
188 qi->tqi_cwmax = INIT_CWMAX;
189 qi->tqi_shretry = INIT_SH_RETRY;
190 qi->tqi_lgretry = INIT_LG_RETRY;
191 qi->tqi_physCompBuf = 0;
193 qi->tqi_physCompBuf = qInfo->tqi_compBuf;
204 setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
234 HAL_TX_QUEUE_INFO *qi;
241 qi = &ahp->ah_txq[q];
242 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
250 qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
256 setTxQInterrupts(ah, qi);
272 HAL_TX_QUEUE_INFO *qi;
280 qi = &ahp->ah_txq[q];
281 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
289 if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
302 cwMin = qi->tqi_cwmin;
307 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
308 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
314 | SM(qi->tqi_lgretry, AR_D_RETRY_LIMIT_FR_LG)
315 | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)
332 if (qi->tqi_cbrPeriod) {
334 SM(qi->tqi_cbrPeriod,AR_Q_CBRCFG_CBR_INTERVAL)
335 | SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_CBR_OVF_THRESH));
337 if (qi->tqi_cbrOverflowLimit)
340 if (qi->tqi_readyTime) {
342 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT)
347 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR)
348 | (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
350 if (qi->tqi_readyTime &&
351 (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE))
353 if (qi->tqi_qflags & HAL_TXQ_DBA_GATED)
359 if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_BEMPTY)
363 if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_QEMPTY)
369 if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE)
371 if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE)
373 if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_GLOBAL)
376 else if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_INTRA)
379 if (qi->tqi_qflags & HAL_TXQ_IGNORE_VIRTCOL)
382 if (qi->tqi_qflags & HAL_TXQ_SEQNUM_INC_DIS)
390 switch (qi->tqi_type) {
412 if (!qi->tqi_readyTime) {
439 if (qi->tqi_physCompBuf) {
440 HALASSERT(qi->tqi_type == HAL_TX_QUEUE_DATA ||
441 qi->tqi_type == HAL_TX_QUEUE_UAPSD);
443 OS_REG_WRITE(ah, AR_Q_CBBA, qi->tqi_physCompBuf);
460 if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE)
464 if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE)
468 if (qi->tqi_qflags & HAL_TXQ_TXDESCINT_ENABLE)
472 if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE)
476 if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE)
480 setTxQInterrupts(ah, qi);