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31 #define	AR_NUM_GPIO	6		/* 6 GPIO pins */
32 #define	AR5312_GPIOD_MASK	0x0000002F	/* GPIO data reg r/w mask */
35  * Configure GPIO Output lines
38 ar5312GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
42 	HALASSERT(gpio < AR_NUM_GPIO);
45 		  (OS_REG_READ(ah, gpioOffset+AR5312_GPIOCR) &~ AR_GPIOCR_CR_A(gpio))
46 		| AR_GPIOCR_CR_A(gpio));
52  * Configure GPIO Input lines
55 ar5312GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
59 	HALASSERT(gpio < AR_NUM_GPIO);
62 		  (OS_REG_READ(ah, gpioOffset+AR5312_GPIOCR) &~ AR_GPIOCR_CR_A(gpio))
63 		| AR_GPIOCR_CR_N(gpio));
72 ar5312GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
77 	HALASSERT(gpio < AR_NUM_GPIO);
80 	reg &= ~(1 << gpio);
81 	reg |= (val&1) << gpio;
91 ar5312GpioGet(struct ath_hal *ah, uint32_t gpio)
95 	if (gpio < AR_NUM_GPIO) {
97 		val = ((val & AR5312_GPIOD_MASK) >> gpio) & 0x1;
105  * Set the GPIO Interrupt
108 ar5312GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
113 	/* XXX bounds check gpio */
115 	val &= ~(AR_GPIOCR_CR_A(gpio) |
117 	val |= AR_GPIOCR_CR_N(gpio) | AR_GPIOCR_INT(gpio) | AR_GPIOCR_INT_ENA;