Lines Matching defs:ah
21 #include "ah.h"
33 static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
34 static void ar5416WriteIni(struct ath_hal *ah,
36 static void ar5416SpurMitigate(struct ath_hal *ah,
40 ar5416AniSetup(struct ath_hal *ah)
61 ar5212AniAttach(ah, &aniparams, &aniparams, AH_FALSE);
72 struct ath_hal *ah;
76 ah = &ahp->ah_priv.h;
79 ah->ah_magic = AR5416_MAGIC;
80 ah->ah_getRateTable = ar5416GetRateTable;
81 ah->ah_detach = ar5416Detach;
84 ah->ah_reset = ar5416Reset;
85 ah->ah_phyDisable = ar5416PhyDisable;
86 ah->ah_disable = ar5416Disable;
87 ah->ah_configPCIE = ar5416ConfigPCIE;
88 ah->ah_perCalibration = ar5416PerCalibration;
89 ah->ah_perCalibrationN = ar5416PerCalibrationN;
90 ah->ah_resetCalValid = ar5416ResetCalValid;
91 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit;
92 ah->ah_setTxPower = ar5416SetTransmitPower;
93 ah->ah_setBoardValues = ar5416SetBoardValues;
96 ah->ah_stopTxDma = ar5416StopTxDma;
97 ah->ah_setupTxDesc = ar5416SetupTxDesc;
98 ah->ah_setupXTxDesc = ar5416SetupXTxDesc;
99 ah->ah_fillTxDesc = ar5416FillTxDesc;
100 ah->ah_procTxDesc = ar5416ProcTxDesc;
103 ah->ah_startPcuReceive = ar5416StartPcuReceive;
104 ah->ah_stopPcuReceive = ar5416StopPcuReceive;
105 ah->ah_setupRxDesc = ar5416SetupRxDesc;
106 ah->ah_procRxDesc = ar5416ProcRxDesc;
107 ah->ah_rxMonitor = ar5416AniPoll;
108 ah->ah_procMibEvent = ar5416ProcessMibIntr;
111 ah->ah_getDiagState = ar5416GetDiagState;
112 ah->ah_setLedState = ar5416SetLedState;
113 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput;
114 ah->ah_gpioCfgInput = ar5416GpioCfgInput;
115 ah->ah_gpioGet = ar5416GpioGet;
116 ah->ah_gpioSet = ar5416GpioSet;
117 ah->ah_gpioSetIntr = ar5416GpioSetIntr;
118 ah->ah_resetTsf = ar5416ResetTsf;
119 ah->ah_getRfGain = ar5416GetRfgain;
120 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch;
121 ah->ah_setDecompMask = ar5416SetDecompMask;
122 ah->ah_setCoverageClass = ar5416SetCoverageClass;
124 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry;
125 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry;
128 ah->ah_setPowerMode = ar5416SetPowerMode;
131 ah->ah_setBeaconTimers = ar5416SetBeaconTimers;
132 ah->ah_beaconInit = ar5416BeaconInit;
133 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers;
134 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers;
138 ah->ah_chainTxDesc = ar5416ChainTxDesc;
139 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc;
140 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc;
141 ah->ah_set11nRateScenario = ar5416Set11nRateScenario;
142 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle;
143 ah->ah_clr11nAggr = ar5416Clr11nAggr;
144 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration;
145 ah->ah_get11nExtBusy = ar5416Get11nExtBusy;
146 ah->ah_set11nMac2040 = ar5416Set11nMac2040;
147 ah->ah_get11nRxClear = ar5416Get11nRxClear;
148 ah->ah_set11nRxClear = ar5416Set11nRxClear;
152 ah->ah_isInterruptPending = ar5416IsInterruptPending;
153 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts;
154 ah->ah_setInterrupts = ar5416SetInterrupts;
168 AH5416(ah)->ah_writeIni = ar5416WriteIni;
169 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate;
173 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK;
174 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;
178 ar5416GetRadioRev(struct ath_hal *ah)
184 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
186 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
187 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
201 struct ath_hal *ah;
222 ah = &ahp->ah_priv.h;
224 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
226 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__);
231 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
232 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__);
237 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
238 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
239 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
240 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE);
246 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3);
247 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2);
248 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2);
249 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2);
250 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3);
251 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3);
252 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2);
253 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2);
255 if (!IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */
261 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac));
262 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1];
263 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0;
266 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2);
267 ar5416AttachPCIE(ah);
269 ecode = ath_hal_v14EepromAttach(ah);
273 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
274 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
280 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
282 if (!ar5212ChipTest(ah)) {
283 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
293 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
296 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
297 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
304 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
311 AH_PRIVATE(ah)->ah_analog5GhzRev =
317 HALDEBUG(ah, HAL_DEBUG_ANY,
320 AH_PRIVATE(ah)->ah_analog5GhzRev);
329 if (!ar5416FillCapabilityInfo(ah)) {
334 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
336 HALDEBUG(ah, HAL_DEBUG_ANY,
342 AH_PRIVATE(ah)->ah_currentRD =
343 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
352 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
354 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: Attaching AR2133 radio\n",
356 rfStatus = ar2133RfAttach(ah, &ecode);
358 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
363 ar5416AniSetup(ah); /* Anti Noise Immunity */
364 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
366 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
368 return ah;
378 ar5416Detach(struct ath_hal *ah)
380 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
382 HALASSERT(ah != AH_NULL);
383 HALASSERT(ah->ah_magic == AR5416_MAGIC);
385 ar5416AniDetach(ah);
386 ar5212RfDetach(ah);
387 ah->ah_disable(ah);
388 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
389 ath_hal_eepromDetach(ah);
390 ath_hal_free(ah);
394 ar5416AttachPCIE(struct ath_hal *ah)
396 if (AH_PRIVATE(ah)->ah_ispcie)
397 ath_hal_configPCIE(ah, AH_FALSE);
399 ath_hal_disablePCIE(ah);
403 ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
405 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
406 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
408 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
409 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
414 ar5416WriteIni(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
439 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
444 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
447 ar5416EepromSetAddac(ah, chan);
449 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1,
451 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
453 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
455 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
459 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
468 ar5416SpurMitigate(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
470 uint16_t freq = ath_hal_gethwchannel(ah, chan);
502 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
516 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
522 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new);
529 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new);
548 OS_REG_WRITE(ah, AR_PHY_TIMING11, new);
576 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
577 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
627 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
628 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
638 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
639 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
649 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
650 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
660 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
661 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
671 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
672 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
682 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
683 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
693 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
694 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
704 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
705 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
714 ar5416FillCapabilityInfo(struct ath_hal *ah)
716 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
722 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
729 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) {
750 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
754 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
777 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
782 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
816 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL);
818 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL);
825 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
826 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
Indexes created Sat Oct 25 16:10:12 GMT 2025