Cross Reference: /src/sys/external/isc/atheros_hal/dist/ar5416/ar5416

Lines Matching refs:SM
352 	powerVal = SM(ackTpcPow, AR_TPC_ACK) |
353 		SM(ctsTpcPow, AR_TPC_CTS) |
354 		SM(chirpTpcPow, AR_TPC_CHIRP);
509 		    SM(ahp->ah_txTrigLev, AR_FTRIG));
604 		SM(2, AR_NOACK_2BIT_VALUE) |
605 		SM(5, AR_NOACK_BIT_OFFSET) |
606 		SM(0, AR_NOACK_BYTE_OFFSET));
1188 		pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
1191 			pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
1193 			pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
1197 			pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV);
1212 			pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
1215 		pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
1218 			pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
1220 			pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
1223 			pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV);
1225 			pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV);
1231 			pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1233 			pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1236 			pll |= SM(0xa, AR_RTC_PLL_DIV);
1238 			pll |= SM(0xb, AR_RTC_PLL_DIV);
1293         	SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1294         	SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1304 			SM(IS_EEP_MINOR_V3(ah)  ? pModal->txRxAttenCh[i] : txRxAttenLocal,
1309 			SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
1317         SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
1318         | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
1319         | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
1320         | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1352 			SM(pModal->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1354 			SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1356 			SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1358 			SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1361 			SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1363 			SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1365 			SM(pModal->bswMargin[2],AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1367 			SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1864 	SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) |
1865 	SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(xpdGainValues[2],  AR_PHY_TPCRG1_PD_GAIN_3));
1900                      SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
1901                      SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)  |
1902                      SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)  |
1903                      SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)  |
1904                      SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
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