Lines Matching defs:ah
21 #include "ah.h"
63 static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
64 static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah);
65 static void ar9280WriteIni(struct ath_hal *ah,
69 ar9280AniSetup(struct ath_hal *ah)
72 ar5212AniAttach(ah, AH_NULL, AH_NULL, AH_FALSE);
84 struct ath_hal *ah;
101 ah = &ahp->ah_priv.h;
103 ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
107 ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch;
108 ah->ah_configPCIE = ar9280ConfigPCIE;
110 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
111 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
112 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
113 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
114 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
116 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
117 AH5416(ah)->ah_writeIni = ar9280WriteIni;
118 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK;
119 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK;
121 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
123 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
129 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
130 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
136 val = OS_REG_READ(ah, AR_SREV);
137 HALDEBUG(ah, HAL_DEBUG_ATTACH,
142 AH_PRIVATE(ah)->ah_macVersion =
144 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
145 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
148 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
151 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
158 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
161 ar5416AttachPCIE(ah);
163 ecode = ath_hal_v14EepromAttach(ah);
167 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
168 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
173 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
175 if (!ar5212ChipTest(ah)) {
176 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
186 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
189 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
190 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
195 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
196 AH_PRIVATE(ah)->ah_analog5GhzRev =
201 HALDEBUG(ah, HAL_DEBUG_ANY,
204 AH_PRIVATE(ah)->ah_analog5GhzRev);
209 rfStatus = ar9280RfAttach(ah, &ecode);
211 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
216 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
218 switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) {
236 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
238 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
256 if (!ar9280FillCapabilityInfo(ah)) {
261 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
263 HALDEBUG(ah, HAL_DEBUG_ANY,
269 AH_PRIVATE(ah)->ah_currentRD =
270 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
279 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
281 ar9280AniSetup(ah); /* Anti Noise Immunity */
282 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
284 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
286 return ah;
288 if (ah != AH_NULL)
289 ah->ah_detach(ah);
296 ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
298 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
299 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
301 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
302 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
307 ar9280WriteIni(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
330 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
331 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
335 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
337 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
338 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain,
340 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,
344 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
347 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
349 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes,
360 ar9280SpurMitigate(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
390 ar5416GetChannelCenters(ah, chan, ¢ers);
398 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
429 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
432 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
440 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
445 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
451 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal);
458 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
493 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal);
497 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
525 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
526 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
576 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
577 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
587 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
588 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
598 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
599 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
609 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
610 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
620 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
621 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
631 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
632 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
642 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
643 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
653 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
654 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
663 ar9280FillCapabilityInfo(struct ath_hal *ah)
665 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
667 if (!ar5416FillCapabilityInfo(ah))
695 ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
699 struct ath_hal_5416 *ahp = AH5416(ah);
710 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK)
Indexes created Sun Oct 26 18:09:56 GMT 2025