Lines Matching defs:expected_fpu
3081 const struct x86_test_fpu_registers expected_fpu = {
3231 set_fpu_regs(&expected_fpu);
3317 FORKEE_ASSERT_EQ(vals_fpu.cw, expected_fpu.cw);
3318 FORKEE_ASSERT_EQ(vals_fpu.sw, expected_fpu.sw);
3319 FORKEE_ASSERT_EQ(vals_fpu.tw, expected_fpu.tw);
3321 expected_fpu.tw_abridged);
3323 expected_fpu.ip.fa_64);
3325 expected_fpu.dp.fa_64);
3328 expected_fpu.st[0].sign_exp);
3330 expected_fpu.st[0].mantissa);
3332 expected_fpu.st[1].sign_exp);
3334 expected_fpu.st[1].mantissa);
3336 expected_fpu.st[2].sign_exp);
3338 expected_fpu.st[2].mantissa);
3340 expected_fpu.st[3].sign_exp);
3342 expected_fpu.st[3].mantissa);
3344 expected_fpu.st[4].sign_exp);
3346 expected_fpu.st[4].mantissa);
3348 expected_fpu.st[5].sign_exp);
3350 expected_fpu.st[5].mantissa);
3352 expected_fpu.st[6].sign_exp);
3354 expected_fpu.st[6].mantissa);
3753 expected_fpu.cw);
3755 expected_fpu.sw);
3757 expected_fpu.tw);
3759 expected_fpu.opcode);
3769 ATF_CHECK_EQ(fxs->fx_cw, expected_fpu.cw);
3770 ATF_CHECK_EQ(fxs->fx_sw, expected_fpu.sw);
3772 expected_fpu.tw_abridged);
3774 expected_fpu.opcode);
3789 ATF_CHECK_EQ(ST_EXP(0), expected_fpu.st[0].sign_exp);
3790 ATF_CHECK_EQ(ST_MAN(0), expected_fpu.st[0].mantissa);
3791 ATF_CHECK_EQ(ST_EXP(1), expected_fpu.st[1].sign_exp);
3792 ATF_CHECK_EQ(ST_MAN(1), expected_fpu.st[1].mantissa);
3793 ATF_CHECK_EQ(ST_EXP(2), expected_fpu.st[2].sign_exp);
3794 ATF_CHECK_EQ(ST_MAN(2), expected_fpu.st[2].mantissa);
3795 ATF_CHECK_EQ(ST_EXP(3), expected_fpu.st[3].sign_exp);
3796 ATF_CHECK_EQ(ST_MAN(3), expected_fpu.st[3].mantissa);
3797 ATF_CHECK_EQ(ST_EXP(4), expected_fpu.st[4].sign_exp);
3798 ATF_CHECK_EQ(ST_MAN(4), expected_fpu.st[4].mantissa);
3799 ATF_CHECK_EQ(ST_EXP(5), expected_fpu.st[5].sign_exp);
3800 ATF_CHECK_EQ(ST_MAN(5), expected_fpu.st[5].mantissa);
3801 ATF_CHECK_EQ(ST_EXP(6), expected_fpu.st[6].sign_exp);
3802 ATF_CHECK_EQ(ST_MAN(6), expected_fpu.st[6].mantissa);
3803 ATF_CHECK_EQ(ST_EXP(7), expected_fpu.st[7].sign_exp);
3804 ATF_CHECK_EQ(ST_MAN(7), expected_fpu.st[7].mantissa);
4015 fpr.fstate.s87_cw = expected_fpu.cw;
4016 fpr.fstate.s87_sw = expected_fpu.sw;
4017 fpr.fstate.s87_tw = expected_fpu.tw;
4018 fpr.fstate.s87_opcode = expected_fpu.opcode;
4019 fpr.fstate.s87_ip = expected_fpu.ip;
4020 fpr.fstate.s87_dp = expected_fpu.dp;
4025 fxs->fx_cw = expected_fpu.cw;
4026 fxs->fx_sw = expected_fpu.sw;
4027 fxs->fx_tw = expected_fpu.tw_abridged;
4028 fxs->fx_opcode = expected_fpu.opcode;
4029 fxs->fx_ip = expected_fpu.ip;
4030 fxs->fx_dp = expected_fpu.dp;
4033 ST_EXP(0) = expected_fpu.st[0].sign_exp;
4034 ST_MAN(0) = expected_fpu.st[0].mantissa;
4035 ST_EXP(1) = expected_fpu.st[1].sign_exp;
4036 ST_MAN(1) = expected_fpu.st[1].mantissa;
4037 ST_EXP(2) = expected_fpu.st[2].sign_exp;
4038 ST_MAN(2) = expected_fpu.st[2].mantissa;
4039 ST_EXP(3) = expected_fpu.st[3].sign_exp;
4040 ST_MAN(3) = expected_fpu.st[3].mantissa;
4041 ST_EXP(4) = expected_fpu.st[4].sign_exp;
4042 ST_MAN(4) = expected_fpu.st[4].mantissa;
4043 ST_EXP(5) = expected_fpu.st[5].sign_exp;
4044 ST_MAN(5) = expected_fpu.st[5].mantissa;
4045 ST_EXP(6) = expected_fpu.st[6].sign_exp;
4046 ST_MAN(6) = expected_fpu.st[6].mantissa;
4047 ST_EXP(7) = expected_fpu.st[7].sign_exp;
4048 ST_MAN(7) = expected_fpu.st[7].mantissa;
Indexes created Wed Oct 01 07:09:59 GMT 2025