Lines Matching defs:smmu
2097 { NDMAC(SMMU), "SMMUv1 or v2", PRFN(smmuv1v2)},
2199 ACPI_IORT_SMMU *smmu = (ACPI_IORT_SMMU *)node->NodeData;
2204 printf("\tBase Address=%016jx\n", (uintmax_t)smmu->BaseAddress);
2205 printf("\tSpan=%016jx\n", (uintmax_t)smmu->Span);
2207 switch (smmu->Model) {
2227 printf("reserved (%u)\n", smmu->Model);
2232 PRINTFLAG(smmu->Flags, DVM_SUPPORTED);
2233 PRINTFLAG(smmu->Flags, COHERENT_WALK);
2238 + smmu->GlobalInterruptOffset);
2246 if (smmu->ContextInterruptCount != 0) {
2248 + smmu->ContextInterruptOffset);
2250 for (i = 0; i < smmu->ContextInterruptCount; i++) {
2256 if (smmu->PmuInterruptCount != 0) {
2258 + smmu->PmuInterruptOffset);
2260 for (i = 0; i < smmu->PmuInterruptCount; i++) {
2271 ACPI_IORT_SMMU_V3 *smmu = (ACPI_IORT_SMMU_V3 *)node->NodeData;
2274 printf("\tBase Address=%016jx\n", (uintmax_t)smmu->BaseAddress);
2277 httuo = __SHIFTOUT(smmu->Flags, ACPI_IORT_SMMU_V3_HTTU_OVERRIDE);
2280 PRINTFLAG(smmu->Flags, HTTU_OVERRIDE);
2281 PRINTFLAG(smmu->Flags, COHACC_OVERRIDE);
2282 PRINTFLAG(smmu->Flags, PXM_VALID);
2285 printf("\tVATOS Address=%016jx\n", (uintmax_t)smmu->VatosAddress);
2287 switch (smmu->Model) {
2292 printf("HiSilicon Hi161x SMMU-v3\n");
2295 printf("Cavium CN99xx SMMU-v3\n");
2298 printf("reserved (%u)\n", smmu->Model);
2302 printf("\tEvent GSIV=%u\n", smmu->EventGsiv);
2303 printf("\tPRI GSIV=%u\n", smmu->PriGsiv);
2304 printf("\tGERR GSIV=%u\n", smmu->GerrGsiv);
2305 printf("\tSync GSIV=%u\n", smmu->SyncGsiv);
2306 printf("\tProximity domain=%u\n", smmu->Pxm);
2309 printf("\tDevice ID mapping index=%u\n", smmu->IdMappingIndex);
Indexes created Fri Oct 03 02:09:57 GMT 2025