Lines Matching defs:AddrSurfInfoIn
293 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
303 AddrSurfInfoIn->mipLevel = level;
304 AddrSurfInfoIn->width = u_minify(config->info.width, level);
305 AddrSurfInfoIn->height = u_minify(config->info.height, level);
311 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
312 AddrSurfInfoIn->bpp &&
313 util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
314 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
316 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
320 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
322 AddrSurfInfoIn->numSlices = 6;
324 AddrSurfInfoIn->numSlices = config->info.array_size;
330 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
332 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
336 AddrSurfInfoIn->basePitch *= surf->blk_w;
340 AddrSurfInfoIn,
377 if (AddrSurfInfoIn->flags.dccCompatible &&
419 AddrSurfInfoIn->flags.depth &&
422 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
633 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
643 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
665 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
668 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
671 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
683 AddrSurfInfoIn.format = ADDR_FMT_BC1;
686 AddrSurfInfoIn.format = ADDR_FMT_BC3;
693 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
696 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
698 AddrSurfInfoIn.tileIndex = -1;
701 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
707 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
709 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
711 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
713 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
714 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
715 AddrSurfInfoIn.flags.cube = config->is_cube;
716 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
717 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
718 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
723 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
724 !AddrSurfInfoIn.flags.fmask &&
734 AddrSurfInfoIn.flags.dccCompatible =
742 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
743 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
764 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
769 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
772 AddrSurfInfoIn.flags.noStencil = 1;
777 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
788 AddrSurfInfoIn.flags.opt4Space = 0;
789 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
791 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
800 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
803 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
805 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
807 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
810 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
812 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
814 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
816 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
820 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
821 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
823 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
846 &AddrSurfInfoIn, &AddrSurfInfoOut,
858 !AddrSurfInfoIn.flags.tcCompatible ||
859 AddrSurfInfoIn.flags.matchStencilTileCfg);
861 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
863 AddrSurfInfoIn.flags.tcCompatible = 0;
867 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
868 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
883 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
884 AddrSurfInfoIn.bpp = 8;
885 AddrSurfInfoIn.flags.depth = 0;
886 AddrSurfInfoIn.flags.stencil = 1;
887 AddrSurfInfoIn.flags.tcCompatible = 0;
888 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
893 &AddrSurfInfoIn, &AddrSurfInfoOut,
927 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color) {
938 fin.numSlices = AddrSurfInfoIn.numSlices;
939 fin.numSamples = AddrSurfInfoIn.numSamples;
940 fin.numFrags = AddrSurfInfoIn.numFrags;
1464 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1467 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1476 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1479 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1488 AddrSurfInfoIn.format = ADDR_FMT_8;
1493 AddrSurfInfoIn.format = ADDR_FMT_16;
1498 AddrSurfInfoIn.format = ADDR_FMT_32;
1502 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1506 AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
1510 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1515 AddrSurfInfoIn.bpp = surf->bpe * 8;
1519 AddrSurfInfoIn.flags.color = is_color_surface &&
1521 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1522 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1524 AddrSurfInfoIn.flags.texture = is_color_surface ||
1526 AddrSurfInfoIn.flags.opt4space = 1;
1528 AddrSurfInfoIn.numMipLevels = config->info.levels;
1529 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1530 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1533 AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
1539 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1541 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1543 AddrSurfInfoIn.width = config->info.width;
1544 AddrSurfInfoIn.height = config->info.height;
1547 AddrSurfInfoIn.numSlices = config->info.depth;
1549 AddrSurfInfoIn.numSlices = 6;
1551 AddrSurfInfoIn.numSlices = config->info.array_size;
1554 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1555 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1565 AddrSurfInfoIn.flags.display) {
1566 AddrSurfInfoIn.flags.metaPipeUnaligned = 1;
1567 AddrSurfInfoIn.flags.metaRbUnaligned = 1;
1574 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1580 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1584 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1585 false, &AddrSurfInfoIn.swizzleMode);
1594 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1612 &AddrSurfInfoIn);
1618 AddrSurfInfoIn.flags.stencil = 1;
1619 AddrSurfInfoIn.bpp = 8;
1620 AddrSurfInfoIn.format = ADDR_FMT_8;
1622 if (!AddrSurfInfoIn.flags.depth) {
1623 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1624 false, &AddrSurfInfoIn.swizzleMode);
1628 AddrSurfInfoIn.flags.depth = 0;
1631 &AddrSurfInfoIn);